Renesas Hitachi H8S/2194 Series Hardware Manual page 256

(2) External Clock
The external clock signal should have the same frequency as the system clock (φ).
Table 10.3 and figure 10.6 show the input conditions for the external clock.
Table 10.3 External Clock Input Conditions
Item
External clock input low
pulse width
External clock input
high pulse width
External clock rise time
External clock fall time
OSC1
Table 10.4 shows the external clock output settling delay time, and figure 10.7 shows the
external clock output settling delay timing. The oscillator and duty adjustment circuit have a
function for adjusting the waveform of the external clock input at the OSC1 pin. When the
prescribed clock signal is input at the OSC1 pin, internal clock signal output is fixed after the
elapse of the external clock output settling delay time (t
fixed during the t
DEXT
V = 4.0 to 5.5 V
CC
Symbol Min
t 40
CPL
t 40
CPH

t
CPr

t
CPf
t
CPH
t
CPr
Figure 10.6 External Clock Input Timing
period, the reset signal should be driven low to maintain the reset state.
Max Unit

ns

ns
10 ns
10 ns
t
CPL
t
CPf
). As the clock signal output is not
DEXT
Rev. 2.0, 11/00, page 229 of 1037
Test Conditions
Figure 10.6