Renesas Hitachi H8S/2194 Series Hardware Manual page 792

The X-value is updated by REF30P. Modification of XDR must be performed
before REF30P in the cycle in which the X-value is changed.
VD
REF30P
HSW
Capstan phase control
ASM mode, PB mode: REF30X-PB-CTL
REF30X
PB-CTL
CTL
16bit
/4
UP/DOWN
counter
0 pulse
DVCFG2
CREF
Ta is the interval calculated from RDCR3.
Tb is the interval in which switchover is
performed from ASM mode to REC mode.
Tx is the cycle in which the REF30X period
is shortened due to the change of XDR.
Figure 28.51 Example of CTLM Switchover Timing
(When Phase Control is Performed by CREF and DVCFG2 in REC Mode)
X-value (XDR) is
rewritten in this
cycle
X-value after
change
X value
Tx
Ta Tb
/5
UDF
1 pulse
CDIVR2
Register write
ASM-REC
switchover
Capstan phase control
REC mode : REF30P-DVCFG2
REC-CTL
/4
RCDR1 RCDR3 RCDR1 RCDR2
0 pulse 1 pulse
Latch
With CREF and DVCFG2
phase alignment, the
frequency need not be 25 Hz
or 30 Hz.
Rev. 2.0, 11/00, page 765 of 1037
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