Section 10 Clock Pulse Generator; Overview; Block Diagram; Register Configuration - Renesas Hitachi H8S/2194 Series Hardware Manual

Section 10 Clock Pulse Generator

10.1

Overview

This LSI has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock
selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit.
10.1.1

Block Diagram

Figure 10.1 shows a block diagram of the clock pulse generator.
System
OSC1
clock
oscillator
OSC2
X1
Subclock
oscillator
X2
Figure 10.1 Block Diagram of Clock Pulse Generator
10.1.2

Register Configuration

The clock pulse generator is controlled by SBYCR and LPWRCR. Table 10.1 shows the register
configuration.
Table 10.1 CPG Registers
Name
Standby control register
Low-power control
register
Note: Lower 16 bits of the address.
*
Duty
Medium-
adjustment
speed clock
circuit
divider
SUB
Subclock
division
circuit
Timer A
count clock
Abbreviation
SBYCR
LPWRCR
or
Clock
selection
circuit
Internal clock
To supporting modules
SUB ( w/2, w/4, w/8)
R/W Initial Value
R/W H'00
R/W H'00
Rev. 2.0, 11/00, page 223 of 1037
/16, /32, /64
w/2, w/4, w/8
SUB
Bus master clock
To CPU
Address*
H'FFEA
H'FFEB