Renesas Hitachi H8S/2194 Series Hardware Manual page 5

Main Revisions and Additions in this Edition
Page Item
All pages of
this manual
5 1.1 Overview
14 1.4 Differences between
H8S/2194C Series and
H8S/2194 Series
All pages of
section 2
31 2.6.1 Overview
65, 66 3.4 Address Map in Each
Operating Mode
68 4.1 Overview
79 4.4.1 Sleep Mode
80 4.5.1 Module Stop Mode
119
6.4.5 Interrupt Response
Times
121 6.5.4 When NMI is Disabled
126 7.2.3 Flash Memory
Operating Modes
127
131
7.3.1 Flash Memory Control
Register 1 (FLMCR1)
Revisions (See Manual for Details)
Amendments due to introduction of the H8S/2194C
series
Table 1.1 Features
Memory and Product lineup amended
Added
Notes on TAS instruction added
Table 2.1 Instruction Classification
Notes 3 added
Address maps for the H8S/2194C series added
Table 4.1 Internal Chip Status in Each Mode
Timer L, PSU, 12-bit PWM added
Sleep and Watch modes of I/O amended
Description amended
Other supporting modules (excluding the servo
circuit and 12-bit PWM) do not stop.
Table 4.4 MSTP Bits and Corresponding On-Chip
Supporting Modules
Module corresponding to the MSTP1 bit amended
Table 6.8 Interrupt Response Times
Note 2 amended
Added
Figure 7.3 Flash Memory Mode Transitions
Amended
Figure 7.4 Boot Mode
Amended
Description amended
FLMCR1 is initialized by a reset, in power-down
state (excluding the medium-speed mode, module
stop mode, and sleep mode), or when a low level is
input to the FWE pin.
Rev. 2.0, 11/00, page I of V