Renesas Hitachi H8S/2194 Series Hardware Manual page 623

(2) Figure 27.3 shows the operation when the instruction immediately preceding the trap address
is that of 2 states or more of the execution cycle and the next instruction prefetch occurs in
the second state from the last. The address to be stacked is 0268.
MOV
instruc-
tion
pre-fetch
Address bus
0266
Interrupt
request
signal
(3) Figure 27.4 shows the operation when the instruction immediately preceding the trap address
is that of 1 state or 2 states or more and the prefetch occurs in the last state. The address to
be stacked is 025C.
NOP
instruc-
tion
pre-fetch
Address bus
0256
Interrupt
request
signal
Rev. 2.0, 11/00, page 596 of 1037
Start of exception
Data
NOP NOP
read
instruc- instruc-
handling
tion tion
pre-fetch pre-fetch
0268 0000 026A
NOP
MOV
execution
execution
Figure 27.3 Basic Operations (2)
Start of
NOP NOP NOP
instruc- instruc- instruc-
exception
tion tion tion
handling
pre-fetch pre-fetch pre-fetch
0258 025A 025C
NOP NOP NOP
execu- execu- execu-
tion tion tion
Figure 27.4 Basic Operations (3)
Immediately
preceding
instruction
026C
Immediately
preceding
instruction
025E
Address
0266 MOV.B R2L, @0000
*
0268 NOP
026A NOP
026C NOP
* Trap setting address
The underlines address is the
one to be actually stacked.
Address
0256 NOP
*
0258 NOP
025A NOP
025C NOP
025E NOP
* Trap setting address
The underlines address is the
one to be actually stacked.