Renesas Hitachi H8S/2194 Series Hardware Manual page 712

(2) DFG Speed Error Data Register (DFER)
Bit : 15
Initial value :
0
R/W :
R * /W
Note: * Note that only detected error data can be read.
DFER is a register that stores 16-bit DFG speed error data. When the drum motor speed is
correct, the data latched in DFER is H'0000. Negative data will be latched if the speed is too
fast, and positive data if the speed is too slow. The DFER value is sent to the digital filter either
automatically or by software.
DFER is a 16-bit readable/writable register. DFER is accessible by word access only. Byte
access gives unassured results. DFER is initialized to H'0000 by a reset, and in standby mode
and module stop mode.
Refer to the Note in 28.6.4 (1) Specified DFG Speed Preset Data Register (DFPR).
(3) DFG Lock UPPER Data Register (DFRUDR)
Bit : 15
Initial value :
0
R/W :
W
DFRUDR is a register used to set the lock range on the UPPER side when drum speed lock is
detected, and to set the limit value on the UPPER side when the limiter function is in use. Set a
signed data to DFRUDR (bit 15 is a sign-setting bit).
When lock is being detected, if the drum speed is detected within the lock range, the lock
counter which has been set by DFRCS 1 and 0 bits of the DFVCR register counts down. If the
set value of DFRCS 1 and 0 matches the number of times of occurrence of locking, the
computation of the digital filter in the drum phase system can be controlled automatically. Also,
if the DFG speed error data is beyond the DFRUDR value while the limiter function is in use,
the DFRUDR value can be used as the data for computation by the digital filter.
DFRUDR is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined
value is read out. It is initialized to H'7FFF by a reset, stand-by or module-stop.
14 13 12 11 10
0 0 0 0 0
R * /W R * /W R * /W R * W R * /W
14 13 12 11 10
1 1 1 1 1
W W W W W
9 8 7 6 5
0 0 0 0 0
R * /W R * /W R * /W R * /W R * /W R * /W
9 8 7 6 5
1 1 1 1 1
W W W W W
Rev. 2.0, 11/00, page 685 of 1037
4 3 2 1 0
0 0 0 0 0
R * /W R * /W R * /W R * /W
4 3 2 1 0
1 1 1 1 1
W W W W W