Renesas Hitachi H8S/2194 Series Hardware Manual page 584

Slave receive mode
SCL
(Master output) 8 9
SCL
(Slave output)
SDA
A
(Slave output)
[2]
SDA
(Master output)
R/W
TDRE
Interrupt
IRIC
request
generated
ICDRT
ICDRS
[3] Clear IRIC
User
processing
Figure 25.11 Example of Timing in Slave Transmit Mode (MLS = 0)
Slave transmit mode
1 2 3
Bit 7 Bit 6 Bit 5
Interrupt
request
generated
Data 1
Data 1
[3] Write ICDR [3] Write ICDR
4 5 6 7
Bit 4 Bit 3 Bit 2 Bit 1
Data 1
Data 2
[5] Clear IRIC
Rev. 2.0, 11/00, page 557 of 1037
8 9 1 2
Bit 0 Bit 7 Bit 6
Data 2
A
[3]
Interrupt
request
generated
Data 2
[5] Write ICDR