Renesas Hitachi H8S/2194 Series Hardware Manual page 971

H'D096: Reference Frequency Mode Register RFM: Reference Signal Generator
Bit : 7
RCS
Initial value : 0
W
R/W :
Mode select bit
0 Manual mode
1 Auto mode
Clock source select bit
0 φs/2
1 φs/4
H'D097: Reference Frequency Mode Register 2 RFM2: Reference Signal Generator
Bit :
7
(TBC) *
Initial value :
1
(R/W) *
R/W :
TBC select bit
Reference signal is generated with VD
0
Reference signal is generated in free-run
1
Note: * The TBC bit is readable/writable only in the
H8S/2194C series. This bit cannot be
modified in the H8S/2194 series, and the
reference signal is therefore generated in
free-run.
Rev. 2.0, 11/00, page 944 of 1037
6 5 4
VNA CVS REX
0 0 0
W W W
External signal synchronization select bit
0 VD signal or free-run
1 External signal sync
Manual select bit
0 VD sync
1 Free-run
6 5 4
— — —
1 1 1
— — —
3 2
CRD OD/EV
0 0
W W
VideoFF counter set
0 VideoFF signal turns counter set OFF
1 VideoFF signal turns counter set OFF
ODD/EVEN edge switchoverselect bit
0 Generated at field signal rising (EVEN)
1 Generated at field signal rising (ODD)
DVCFG2 synchronization select bit
0 At mode switching
1 DVCFG2 signal synchronized
3 2
— —
1 1
— —
Field select bit
0 Generated by selected ODD or EVEN VD
1 Generated by VD signal immediately after
1 0
VST VEG
0 0
W W
VideoFF edge select bit
0 Set at VideoFF signal rising
1 Set at VideoFF signal falling
1 0
— FDS
1 0
—
R/W
signal
mode transition