Renesas Hitachi H8S/2194 Series Hardware Manual page 338

Bits 5 and 4: Selecting the Monitor Signals (MON1 or MON0)
These bits work to select the type of signals being output through the BUZZ pin for monitoring
purpose. These settings are valid only when the BUZZ1 and BUZZ0 bits are being set to 1 and
0.
When PB-CTL or REC-CTL is chosen, signal duties will be output as they are.
In case of DVCTL signals, signals from the CTL dividing circuit will be toggled before being
output. Signal waveforms divided by the CTL dividing circuit into "n-divisions" will further be
divided into halves. (Namely, "2n" divisions, 50% duty waveform).
In case of TCA7, Bit 7 of the counter of the Timer A will be output. (50% duty)
When the prescaler is being used with the Timer A, 1Hz outputs are available.
Bit 5 Bit 4
MON1 MON0
0 0
1
1 *
Note: Don't care.
*
Bits 3: Reserved
When this is read, 1 will always be readout. Writes are disabled.
Bit 2: Enabling Interrupt of the TMJ2I (TMJ2IE)
This bit works to permit/prohibit occurrence of TMJ2I interrupt of the TMJS in 1-set of the
TMJ2I.
Bit 2
TMJ2IE Description
0 Prohibits occurrence of TMJ2I interrupt
1 Permits occurrence of TMJ2I interrupt
Bit 1: Enabling Interrupt of the TMJ1I (TMJ1IE)
This bit works to permit/prohibit occurrence of TMJ1I interrupt of the TMJS in 1-set of the
TMJ1I.
Bit 1
TMJ1IE Description
0 Prohibits occurrence of TMJ1I interrupt
1 Permits occurrence of TMJ1I interrupt
Description
PB or REC-CTL
DVCTL
Outputs TCA7
(Initial value)
(Initial value)
(Initial value)
Rev. 2.0, 11/00, page 311 of 1037