Servo Interrupt; 28.16.1 Overview; Register Configuration; Register Description - Renesas Hitachi H8S/2194 Series Hardware Manual

28.16

Servo Interrupt

28.16.1 Overview

The interrupt exception processing of the servo module is started by one of ten factors, i.e. the
drum speed error detector (×2), drum phase error detector, capstan speed error detector (×2),
capstan phase error detector, HSW timing generator (×2), sync detector and CTL circuit. For
these interrupt factors, see each of their circuit sections in this manual.
Also, see section 5, Exception Handling.

28.16.2 Register Configuration

Table 28.27 shows the list of the registers which control the interrupt of the servo section.
Table 28.27 Registers which Control the Interrupt of the Servo Section
Name
Servo interrupt
permission register 1
Servo interrupt
permission register 2
Servo interrupt request
register 1
Servo interrupt request
register 2

28.16.3 Register Description

(1) Servo Interrupt Permission Register 1 (SIENR1)
Bit : 7
IEDRM3
0
Initial value :
R/W
R/W :
SIENR1 controls the permission and prohibition of the interrupt of the servo section. SIENR1 is
an 8-bit readable/writable register. It is initialized to H'00 by a reset, stand-by or module stop.
Rev. 2.0, 11/00, page 810 of 1037
Abbrev. R/W
SIENR1 R/W
SIENR2 R/W
SIRQR1 R/W
SIRQR2 R/W
6 5
IEDRM2 IEDRM1 IECAP3
0 0
R/W R/W
Size
Byte
Byte
Byte
Byte
4 3
IECAP2 IECAP1
0 0
R/W R/W R/W
Initial Value Address
H'00 H'FD0B8
H'FC H'FD0B9
H'00 H'FD0BA
H'FC H'FD0BB
2 1 0
IEHSW2 IEHSW1
0 0 0
R/W R/W