Renesas Hitachi H8S/2194 Series Hardware Manual page 627

(4) When the condition is not satisfied by Bcc instruction (Trap address at branch)
When the trap address is at the branch of the Bcc instruction and the condition is not satisfied
by the Bcc instruction and thus it fails to branch, transition is made into the address trap
interrupt after executing the next instruction (if the next instruction is that of 2 states or
more. If the next instruction is that of 1 state, after executing two instructions). The address
to be stacked is 0262.
BEQ
instruc-
tion
pre-fetch
Address bus
025C
Interrupt
request
signal
Figure 27.9 When the Condition is Not Satisfied by Bcc Instruction
Rev. 2.0, 11/00, page 600 of 1037
NOP CMP NOP NOP
instruc- instruc- instruc- instruc-
tion tion tion tion
pre-fetch pre-fetch pre-fetch pre-fetch
025E 0266 0260 0262
BEQ
NOP NOP
execution
execu- execu-
tion tion
(Trap Address at Branch)
Start of
exception
handling
0264
*
NEXT:
* Trap setting address
(NEXT = H'0266)
025C BEQ NEXT:8
025E NOP
0260 NOP
0262 NOP
0264 NOP
0266 CMP.W R0, R1
0268 NOP
The underlines address is the
one to be actually stacked.