Table of Contents
Advertisement
H'D059: Capstan Phase Error Detection Control Register
Bit :
7
CPCS1
Initial value :
0
R/W
R/W :
Clock source select bit
CPCS1 CPCS0
0
1
Note: * Only 0 can be written.
H'D05A: Specified Capstan Phase Preset Data Register 2 CPPR2: Capstan Error Detector
Bit :
15
14
Initial value :
0
0
R/W :
W
W
H'D05C: Specified Capstan Phase Preset Data Register 1 CPPR1: Capstan Error Detector
Bit :
7
—
Initial value :
1
—
R/W :
6
5
CPCS0
CPOVF
0
0
R/(W) *
R/W
Preset signal select bit
0
Preset by REF30P signal
1
Preset by CRRF signal
Counter overflow flag
0
Normal status
1
Counter overflows.
Description
φs
0
φs/2
1
φs/4
0
φs/8
1
13
12
11
10
0
0
0
0
W
W
W
W
6
5
—
—
1
1
—
—
CPGCR: Capstan Error Detector
4
3
CR/RF
SELCFG2
0
0
R/W
R/W
Preset, latch signal select bit
0
Preset by CAPREF30 signal and latch by DVCTL signal
1
Preset by REF30P signal and latch by DVCFG2 signal
9
8
7
6
0
0
0
0
W
W
W
W
4
3
—
1
0
—
W
2
1
0
—
—
—
1
1
1
—
—
—
5
4
3
2
0
0
0
0
W
W
W
W
W
2
1
0
0
W
W
Rev. 2.0, 11/00, page 929 of 1037
1
0
0
0
W
0
0
W
Advertisement
Table of Contents
