Renesas Hitachi H8S/2194 Series Hardware Manual page 780

Bit
REC FW/
! !
ASM / RV
0 0 0/1
0 1 0
0 0 0
0 0 0
1 0 0/1
0 1 0
MD4 MD3 MD2
0 1 0
0 0 1
0 0 1
1 0 0
0 0 0
1 0 0
MD1 MD0 Mode
0 1 VISS
detect
(index
detect)
0 1 VISS
record
(index
record)
0 1 VISS
rewrite
0 0 VISS
initialize
0 0 ASM
mark
detect
0 0 ASM
mark
record
Description
• The duty I/O flag is set to 1 at the
point of write access to register
CTLM
• The 1 pulses recognized by the
duty discrimination circuit are
counted in the VISS control
circuit
• The duty I/O flag is cleared to 0,
indicating VISS detection, when
the value set at VCTR register is
repeatedly detected
• An interrupt request is generated
when VISS is detected
• 64 pulse data with 0 pulse data at
both edges are written (index
record)
• The index bit string is written
through the duty I/O flag
• An interrupt request is generated
at the end of VISS recording
Same as above (VISS record;
trapezoid waveform circuit
operation)
VISS write is forcibly aborted
ASM mark detection
• The duty I/O flag is cleared to 0
when PB-CTL duty ≥ 66% is
detected
• An interrupt request is generated
when an ASM mark is detected
• An ASM mark is recorded by
writing 0 in the duty I/O flag
• An interrupt is requested for
every one CTL pulse
• REC-CTL is generated and
recorded with the duty cycle set
by register RCDR3
Rev. 2.0, 11/00, page 753 of 1037