Renesas Hitachi H8S/2194 Series Hardware Manual page 778

(2) CTL Mode Register (CTLM)
Bit :
ASM
Initial value :
R/W :
R/W
The CTL mode register (CTLM) is an 8-bit readable/writable register that controls the operating
state of the CTL circuit. If 1 is written in bits MD3 and MD2, they will be cleared to 0 one
cycle (φ) later.
CTLM is initialized to H'00 by a reset, and in standby mode and module stop mode. When CTL
is being stopped, only bits 7, 6 and 5 operate.
Note: Do not set any value other than the setting value for each mode (see table 28.20, CTL
Mode Functions).
Bits 7 and 6: Record/Playback Mode Bits (ASM, REC/PB)
These bits switch between record and playback. Combined with bits 4 to 0 (MD4 to MD0), they
support the VISS, VASS, and ASM mark functions.
Bit 7 Bit 6
ASM REC/
0 0
1
1 0
1
Bit 5: Direction Bit (FW/RV)
Selects the direction in playback. Clear this bit to 0 during record. Figure 28.48 shows the PB-
CTL signal in forward and reverse.
Bit 5
FW/RV Description
0 FORWARD
1 REVERSE
7 6 5
REC/PB FW/RV
0 0 0
R/W R/W
3% 3%
Description
Playback mode
Record mode
Assemble mode
Invalid (do not set)
4 3 2
MD4 MD3 MD2
0 0 0
R/W R/W R/W
Rev. 2.0, 11/00, page 751 of 1037
1 0
MD1 MD0
0 0
R/W R/W
(Initial value)
(Initial value)