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H'D062: HSW Loop Stage Setting Register HSLP: HSW Timing Generator
Bit :
7
LOB3
Initial value :
*
R/W :
R/W
FIFO2 stage setting bit
HSM2
Bit 5
Bit 7
Bit 6
LOP
LOB3
LOB2
0
*
*
1
0
0
1
1
0
1
Note: * Don't care.
6
5
LOB2
LOB1
LOB0
*
*
R/W
R/W
R/W
FIFO1 stage setting bit
HSM2
Bit 5
LOP
0
1
Note: * Don't care.
HSLP
Bit 5
Bit 4
LOB1
LOB0
Single mode
*
*
0
0
Output stage 0 of FIFO2
1
Output stage 0 and 1 of FIFO2
1
0
Output stage 0 to 2 of FIFO2
1
Output stage 0 to 3 of FIFO2
0
0
Output stage 0 to 4 of FIFO2
1
Output stage 0 to 5 of FIFO2
1
0
Output stage 0 to 6 of FIFO2
1
Output stage 0 to 7 of FIFO2
0
0
Output stage 0 to 8 of FIFO2
1
Output stage 0 to 9 of FIFO2
1
0
Setting disabled
1
0
0
1
1
0
1
4
3
2
LOA3
LOA2
*
*
*
R/W
R/W
HSLP
Bit 3
Bit 2
Bit 1
LOA3
LOA2
LOA1
*
*
*
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Description
1
0
LOA1
LOA0
*
*
R/W
R/W
Description
Bit 0
LOA0
Single mode
*
0
Output stage 0 of FIFO1
1
Output stage 0 and 1 of FIFO1
0
Output stage 0 to 2 of FIFO1
1
Output stage 0 to 3 of FIFO1
0
Output stage 0 to 4 of FIFO1
1
Output stage 0 to 5 of FIFO1
0
Output stage 0 to 6 of FIFO1
1
Output stage 0 to 7 of FIFO1
0
Output stage 0 to 8 of FIFO1
1
Output stage 0 to 9 of FIFO1
0
Setting disabled
1
0
1
0
1
Rev. 2.0, 11/00, page 933 of 1037
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