Renesas Hitachi H8S/2194 Series Hardware Manual page 516

In serial transmission, the SCI1 operates as described below.
[1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been
written to TDR1, and transfers the data from TDR1 to TSR.
[2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is
generated.
When clock output mode has been set, the SCI1 outputs 8 serial clock pulses. When use of
an external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the SO1 pin starting with the LSB (bit 0) and ending
with the MSB (bit 7).
[3] The SCI1 checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR1 to TSR, and serial
transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the MSB (bit 7) is sent, and
the SO1 pin maintains its state.
If the TEIE bit in SCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is
generated.
[4] After completion of serial transmission, the SCK1 pin is held in a constant state.
Figure 23.17 shows an example of SCI1 operation in transmission.
Synchronous
clock
Serial
data
TDRE
TEND
TXI interrupt
request
generated
Figure 23.17 Example of SCI1 Operation in Transmission
Transfer
direction
Bit 0 Bit 1
Data written to TDR1
and TDRE flag cleared
to 0 in TXI interrupt
handling routine
1 frame
Bit 7 Bit 0 Bit 1
TXI interrupt
request
generated
Rev. 2.0, 11/00, page 489 of 1037
Bit 6 Bit 7
TEI interrupt
request
generated