Appendix A Instruction Set; Instructions - Renesas Hitachi H8S/2194 Series Hardware Manual

A.1

Instructions

[Operation Notation]
Rd
Rs
Rn
ERn
MAC
(EAd)
(EAs)
EXR
CCR
N
Z
V
C
PC
SP
#IMM
disp
+
−
×
÷
∧
∨
⊕
→
∼
( ) <>
:8/:16/:24/:32

Appendix A Instruction Set

General register (destination)
General register (source)
General register
General register (32-bit register)
Multiplication-Addition register (32-bit register)
Destination operand
Source operand
Extend register
Condition code register
N (negative flag) in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
Stack pointer
Immediate data
Displacement
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
Exclusive logical OR
Move from the left to the right
Logical complement
Contents of operand
8/16/24/32 bit length
*1
*1
*1
Rev. 2.0, 11/00, page 861 of 1037
*2