Renesas Hitachi H8S/2194 Series Hardware Manual page 479

Bit 3: Multiprocessor Interrupt Enable (MPIE)
Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in
asynchronous mode when receiving with the MP bit in SMR1 set to 1.
The MPIE bit setting is invalid in clock synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE Description
0 Multiprocessor interrupts disabled (normal reception performed)
[Clearing conditions]
(1) When the MPIE bit is cleared to 0
(2) When data with MPB = 1 is received
1 Multiprocessor interrupts enabled*
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note: When receive data including MPB = 0 is received, receive data transfer from RSR to
*
RDR1, receive error detection, and setting of the RDRF, FER, and ORER flags in
SSR1, is not performed. When receive data with MPB = 1 is received, the MPB bit in
SSR1 is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and
ERI interrupts (when the TIE and RIE bits in SCR1 are set to 1) and FER and ORER
flag setting is enabled.
Bit 2: Transmit End Interrupt Enable (TEIE)
Enables or disables transmit-end interrupt (TEI) request generation if there is no valid transmit
data in TDR1 when the MSB is transmitted.
Bit 2
TEIE Description
0 Transmit-end interrupt (TEI) request disabled*
1 Transmit-end interrupt (TEI) request enabled*
Note: TEI cancellation can be performed by reading 1 from the TDRE flag in SSR1, then
*
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Bits 1 and 0: Clock Enable 1 and 0 (CKE1, CKE0)
These bits are used to select the SCI1 clock source and enable or disable clock output from the
SCK1 pin. The combination of the CKE1 and CKE0 bits determines whether the SCK1 pin
functions as an I/O port, the serial clock output pin, or the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of
external clock operation (CKE1 = 1). Note that the SCI1's operating mode must be decided
using SMR1 before setting the CKE1 and CKE0 bits.
For details of clock source selection, see table 23.9 in section 23.3, Operation.
Rev. 2.0, 11/00, page 452 of 1037
(Initial value)
(Initial value)