Pin Configuration; Register Configuration - Renesas Hitachi H8S/2194 Series Hardware Manual

14.1.3

Pin Configuration

Table 14.1 shows the pin configuration of the Timer J.
Table 14.1 Pin Configuration
Name
Event input pin
Event input pin
14.1.4

Register Configuration

Table 14.2 shows the register configuration of the Timer J.
The TCJ and TLJ or the TCK and TLK are being allocated to the same address respectively.
Reading or writing determines the accessing register.
Table 14.2 Register Configuration
Name
Timer mode register J
Timer J control register
Timer J status register
Timer counter J
Timer counter K
Timer load register J
Timer load register K
Notes: 1. Only 0 can be written to clear the flag.
2. Lower 16 bits of the address.
Abbrev. I/O
,54
Input
,54
Input
Abbrev. R/W
TMJ R/W
TMJC R/W
*1
TMJS R/(W)
TCJ R
TCK R
TLJ W
TLK W
Function
Event inputs to the TMJ-1
Event inputs to the TMJ-2
Size Initial Value
Byte H'00
Byte H'09
Byte H'3F
Byte H'FF
Byte H'FF
Byte H'FF
Byte H'FF
Rev. 2.0, 11/00, page 305 of 1037
*2
Address
H'D13A
H'D13B
H'D13C
H'D139
H'D138
H'D139
H'D138