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(7) REC-CTL Duty Data Register 5 (RCDR5)
15
Bit :
—
Initial value :
1
R/W :
—
RCDR5 sets the timing of falling edge of the 0 pulse (long) of REC-CTL in record or rewrite
mode. In detection mode, it is used to detect the long/short pulse.
RCDR5 is a 12-bit write-only register. It accepts only a word-access. If a byte access is
attempted, operation is not assured. If a read is attempted, an undefined value is read out. Bits
15 to 12 are reserved, and no write in them is valid.
It is initialized to H'F000 by a reset, stand-by, module stop or CTL stop.
In record mode, set a value with the 62.5% duty cycle obtained from the transition timing T5
corresponding to the servo clock frequency φs according to the following equation. See figure
28.60, REC-CTL Signal Generation Timing.
RCDR5 = T5 × φ s/64
φ is the servo clock frequency (= f
At bit pattern detection, set the 1 pulse long/short threshold value at REV. See figure 28.56,
Duty Discriminator.
RCDR5 = H'FFF − (T5' × φ s/80)
φs is the servo clock frequency (= f
at REV (s).
Rev. 2.0, 11/00, page 758 of 1037
14
13
12
11
10
—
—
—
CMT5B
CMT5A
1
1
1
0
0
—
—
—
W
W
/2) in Hz, and T5 is the set timing (s).
OSC
/2) in Hz, and T5' is the 1 pulse long/short threshold value
OSC
9
8
7
6
5
CMT59
CMT58
CMT57
CMT56
CMT55
0
0
0
0
0
W
W
W
W
W
4
3
2
1
0
CMT54
CMT53
CMT52
CMT51
CMT50
0
0
0
0
0
W
W
W
W
W
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