Renesas Hitachi H8S/2194 Series Hardware Manual page 813

Bit 5: CFG Mask Status Bit (CMK)
Indicates the status of the mask. It is initialized to 1 by a reset, stand-by or module stop.
Bit 5
CMK Description
0 Indicates that the capstan mask timer has released masking
1 Indicates that the capstan mask timer is currently masking
Bit 4: CFG Mask Selection Bit (CMN)
Selects the turning ON/OFF of the mask function.
Bit 4
CMN Description
0 Capstan mask timer function ON
1 Capstan mask timer function OFF
Bit 3: PB (ASM) → REC Transition Timing Sync ON/OFF Selection Bit (DVTRG)
Selects the ON/OFF of the timing sync of the transition from PB (ASM) to REC when the
DVCFG2 signal is generated.
Bit 3
DVTRG Description
PB (ASM) → REC transition timing sync ON
0
PB (ASM) → REC transition timing sync OFF
1
Bit 2: CFG Frequency Division Edge Selection Bit (CRF)
Selects the edge of the CFG signal to be divided.
Bit 2
CRF Description
0 Performs frequency division at the rising edge of CFG
1 Performs frequency division at both edges of CFG
Rev. 2.0, 11/00, page 786 of 1037
(Initial value)
(Initial value)
(Initial value)
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