Table of Contents
Advertisement
28.11
Digital Filters
28.11.1 Overview
The digital filters required in servo control make extensive use of multiply-accumulate
operations on signed integers (error data) and coefficients. A filter computation circuit (digital
filter computation circuit) is provided in on-chip hardware to reduce the load on software, and to
improve processing efficiency. Figure 28.38 shows a block diagram of the digital filter
computation circuit configuration.
The filter computation circuit includes a high-speed 24-bit × 16-bit multiplier-accumulator, an
arithmetic buffer, and an I/O processor. The digital filter computations are carried out by the
high-speed multiplier-accumulator. The arithmetic buffer stores coefficients and gain constants
needed in the filter computations, which are referenced by the high-speed multiplier-
accumulator.
The I/O processor is activated by a frequency generator signal, and determines what operation is
carried out. When activated, it reads the speed error and phase error from the speed and phase
error detectors and sends them to the accumulator.
When the filter computation is completed, the I/O processor reads the result from the
accumulator and sends it to a 12-bit PWM. At this time, the accumulation result gain can be
controlled.
Rev. 2.0, 11/00, page 723 of 1037
Advertisement
Table of Contents
