Page 1 REJ09B0163-0100Z H8S/2111B Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2111B HD64F2111B Rev.1.00 Revision Date: May. 14, 2004...
Page 2 Rev. 1.00, 05/04, page ii of xxxiv...
Page 3 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 4 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 6 Note: * F-ZTAT is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2111B in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
Page 7 Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ H8S/2111B manuals: Document Title H8S/2111B Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual User's manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor...
Page 8 Rev. 1.00, 05/04, page viii of xxxiv...
Page 9: Table Of Contents
Section 1 Overview...1 Features... 1 Internal Block Diagram... 2 Pin Description... 3 1.3.1 Pin Arrangement ... 3 1.3.2 Pin Functions in Each Operating Mode ... 4 1.3.3 Pin Functions ... 9 Section 2 CPU...13 Features... 13 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ... 14 2.1.2 Differences from H8/300 CPU ...
Page 10 Processing States... 46 Usage Notes ... 48 2.9.1 Note on TAS Instruction Usage... 48 2.9.2 Note on STM/LDM Instruction Usage ... 48 2.9.3 Note on Bit Manipulation Instructions ... 48 2.9.4 EEPMOV Instruction... 49 Section 3 MCU Operating Modes ... 51 MCU Operating Mode Selection ...
Page 11 5.4.1 External Interrupts ... 76 5.4.2 Internal Interrupts ... 77 Interrupt Exception Handling Vector Table... 78 Interrupt Control Modes and Interrupt Operation ... 80 5.6.1 Interrupt Control Mode 0 ... 80 5.6.2 Interrupt Control Mode 1 ... 82 5.6.3 Interrupt Exception Handling Sequence ... 85 5.6.4 Interrupt Response Times ...
Page 12 Port 4... 107 7.4.1 Port 4 Data Direction Register (P4DDR)... 107 7.4.2 Port 4 Data Register (P4DR) ... 107 7.4.3 Pin Functions ... 108 Port 5... 110 7.5.1 Port 5 Data Direction Register (P5DDR)... 110 7.5.2 Port 5 Data Register (P5DR) ... 110 7.5.3 Pin Functions ...
Page 13 7.12.5 Pin Functions ... 135 7.12.6 Input Pull-Up MOS in Ports C and D ... 135 7.13 Ports E, F... 136 7.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR) ... 136 7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR) ... 137 7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN)...
Page 14 9.3.7 Timer Control/Status Register (TCSR)... 163 9.3.8 Timer Control Register (TCR)... 166 9.3.9 Timer Output Compare Control Register (TOCR) ... 167 Operation ... 169 9.4.1 Pulse Output ... 169 Operation Timing... 170 9.5.1 FRC Increment Timing... 170 9.5.2 Output Compare Output Timing... 171 9.5.3 FRC Clear Timing ...
Page 15 10.5.1 TCNT Count Timing ... 207 10.5.2 Timing of CMFA and CMFB Setting at Compare-Match ... 207 10.5.3 Timing of Timer Output at Compare-Match... 208 10.5.4 Timing of Counter Clear at Compare-Match ... 208 10.5.5 TCNT External Reset Timing... 209 10.5.6 Timing of Overflow Flag (OVF) Setting ...
Page 16 11.6.5 System Reset by RESO Signal ... 233 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes ... 233 Section 12 Serial Communication Interface (SCI)... 235 12.1 Features... 235 12.2 Input/Output Pins... 236 12.3 Register Descriptions... 237 12.3.1 Receive Shift Register (RSR) ... 237 12.3.2 Receive Data Register (RDR)...
Page 17 12.8.6 SCI Operations during Mode Transitions ... 273 12.8.7 Switching from SCK Pins to Port Pins ... 276 Section 13 I C Bus Interface (IIC) ...277 13.1 Features... 277 13.2 Input/Output Pins ... 280 13.3 Register Descriptions ... 281 13.3.1 I C Bus Data Register (ICDR) ...
Page 18 14.4.6 KBF Setting Timing and KCLK Control... 362 14.4.7 Receive Timing... 363 14.4.8 KCLK Fall Interrupt Operation ... 364 14.5 Usage Notes ... 365 14.5.1 KBIOE Setting and KCLK Falling Edge Detection ... 365 14.5.2 Module Stop Mode Setting ... 366 Section 15 Host Interface (LPC) ...
Page 19 16.4.2 Scan Mode ... 419 16.4.3 Input Sampling and A/D Conversion Time ... 421 16.4.4 External Trigger Input Timing... 422 16.5 Interrupt Sources... 423 16.6 A/D Conversion Accuracy Definitions ... 423 16.7 Usage Notes ... 425 16.7.1 Permissible Signal Source Impedance ... 425 16.7.2 Influences on Absolute Accuracy ...
Page 20 19.2 Duty Correction Circuit ... 459 19.3 Medium-Speed Clock Divider ... 459 19.4 Bus Master Clock Select Circuit... 459 19.5 Subclock Input Circuit ... 460 19.6 Waveform Forming Circuit... 460 19.7 Clock Select Circuit ... 461 19.8 Usage Notes ... 461 19.8.1 Note on Resonator ...
Page 21 22.5 Flash Memory Characteristics ... 527 22.6 Usage Note... 529 22.7 Timing Chart... 529 22.7.1 Clock Timing ... 529 22.7.2 Control Signal Timing ... 531 22.7.3 On-Chip Peripheral Module Timing ... 532 Appendix ...537 I/O Port States in Each Processing State... 537 Product Codes ...
Page 22 Rev. 1.00, 05/04, page xxii of xxxiv...
Page 23 Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ... 43 Figure 2.13 State Transitions ... 47 Section 3 MCU Operating Modes Figure 3.1 Address Map for H8S/2111B-B ... 57 Figure 3.2 Address Map for H8S/2111B-C ... 58 Section 4 Exception Handling Figure 4.1 Reset Sequence (Mode 3)...
Page 24 Section 8 8-Bit PWM Timer (PWM) Figure 8.1 Block Diagram of PWM Timer... 147 Figure 8.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ... 154 Figure 8.3 Example of PWM Setting... 155 Figure 8.4 Example when PWM is Used as D/A Converter... 155 Section 9 16-Bit Free-Running Timer (FRT) Figure 9.1 Block Diagram of 16-Bit Free-Running Timer ...
Page 25 Figure 10.13 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) ... 213 Figure 10.14 Conflict between TCNT Write and Clear... 216 Figure 10.15 Conflict between TCNT Write and Count-Up... 216 Figure 10.16 Conflict between TCOR Write and Compare-Match ... 217 Section 11 Watchdog Timer (WDT) Figure 11.1 Block Diagram of WDT ...
Page 26 Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ... 270 Figure 12.21 Sample Flowchart for Mode Transition during Transmission... 274 Figure 12.22 Pin States during Transmission in Asynchronous Mode (Internal Clock) ... 274 Figure 12.23 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock)...
Page 27 Figure 13.25 IRIC Setting Timing and SCL Control (1) ... 331 Figure 13.26 IRIC Setting Timing and SCL Control (2) ... 332 Figure 13.27 IRIC Setting Timing and SCL Control (3) ... 333 Figure 13.28 Block Diagram of Noise Canceler... 334 Figure 13.29 Notes on Reading Master Receive Data ...
Page 28 Section 16 A/D Converter Figure 16.1 Block Diagram of A/D Converter ... 414 Figure 16.2 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)... 420 Figure 16.3 A/D Conversion Timing... 421 Figure 16.4 External Trigger Input Timing ... 422 Figure 16.5 A/D Conversion Accuracy Definitions ...
Page 29 Figure 22.4 Connection of VCL Capacitor... 529 Figure 22.5 System Clock Timing ... 529 Figure 22.6 Oscillation Settling Timing ... 530 Figure 22.7 Oscillation Setting Timing (Exiting Software Standby Mode)... 530 Figure 22.8 Reset Input Timing... 531 Figure 22.9 Interrupt Input Timing... 531 Figure 22.10 I/O Port Input/Output Timing...
Page 30 Rev. 1.00, 05/04, page xxx of xxxiv...
Page 31 Section 1 Overview Table 1.1 Pin Functions in Each Operating Mode ... 4 Table 1.2 Pin Functions ... 9 Section 2 CPU Table 2.1 Instruction Classification ... 29 Table 2.2 Operation Notation ... 30 Table 2.3 Data Transfer Instructions... 31 Table 2.4 Arithmetic Operations Instructions (1) ...
Page 32 Table 7.4 Input Pull-Up MOS States (Port 3)... 106 Table 7.5 Input Pull-Up MOS States (Port 6)... 116 Table 7.6 Input Pull-Up MOS States (Port A) ... 128 Table 7.7 Input Pull-Up MOS States (Port B) ... 131 Table 7.8 Input Pull-Up MOS States (Port C and port D) ...
Page 33 Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ... 248 Table 12.8 Serial Transfer Formats (Asynchronous Mode)... 250 Table 12.9 SSR Status Flags and Receive Data Handling ... 257 Table 12.10 SCI Interrupt Sources... 271 Section 13 I2C Bus Interface (IIC) Table 13.1 Pin Configuration...
Page 34 Section 19 Clock Pulse Generator Table 19.1 Damping Resistance Values ... 456 Table 19.2 Crystal Resonator Parameters ... 456 Table 19.3 External Clock Input Conditions ... 458 Table 19.4 External Clock Output Stabilization Delay Time ... 458 Table 19.5 Subclock Input Conditions... 460 Section 20 Power-Down Modes Table 20.1 Operating Frequency and Wait Time...
Page 35: Section 1 Overview
Note: 3-V version product • General I/O ports I/O pins: 114 Input-only pins: 8 • Supports various power-down states • Compact package Product Package H8S/2111B TQFP-144 Section 1 Overview 64 Kbytes 64 Kbytes Code TFP-144 Remarks 2 Kbytes 3 Kbytes...
Page 36: Internal Block Diagram
Internal Block Diagram XTAL EXTAL VCCB STBY RESO P97/SDA0 P96/φ/EXCL P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P67/TMOX/KIN7/IRQ7 P66/FTOB/KIN6/IRQ6 P65/FTID/KIN5 P64/FTIC/KIN4 P63/FTIB/KIN3 P62/FTIA/KIN2/TMIY P61/FTOA/KIN1 P60/FTCI/KIN0/TMIX P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SDA1 P41/TMO0 P40/TMCI0 P52/ExSCK1*/SCL0 P51/ExRxD1* P50/ExTxD1* Port 8 Note: * The program development tool (emulator) does not support this function. Rev.
Page 37: Pin Description
Pin Description 1.3.1 Pin Arrangement P12/PW2 P11/PW1 P10/PW0 PB7/WUE7 PB6/WUE6 PB5/WUE5 PB4/WUE4 PB3/WUE3 PB2/WUE2 PB1/WUE1/LSCI PB0/WUE0/LSMI P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37/SERIRQ P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/SCL1 P40/TMCI0 P41/TMO0 P42/TMRI0/SDA1 RESO XTAL EXTAL Note: * The program development tool (emulator) does not support this function. TFP-144 (Top view) Figure 1.2 Pin Arrangement...
Page 38: Pin Functions In Each Operating Mode
1.3.2 Pin Functions in Each Operating Mode Table 1.1 Pin Functions in Each Operating Mode Pin No. Single-Chip Modes TFP-144 Mode 2, Mode 3 (EXPE = 0) P43/TMCI1 P44/TMO1 P45/TMRI1 STBY 14 (N) P52/ExSCK1*/SCL0 P51/ExRxD1* P50/ExTxD1* 17 (N) P97/SDA0 P96/φ/EXCL P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG...
Page 39 Pin No. Single-Chip Modes TFP-144 Mode 2, Mode 3 (EXPE = 0) 33 (B) PA7/KIN15/PS2CD 34 (B) PA6/KIN14/PS2CC 35 (B) PA5/KIN13/PS2BD VCCB 37 (B) PA4/KIN12/PS2BC 38 (B) PA3/KIN11/PS2AD 39 (B) PA2/KIN10/PS2AC 40 (B) PA1/KIN9 41 (B) PA0/KIN8 PF7/TMOY* PF6/ExTMOX* PF5/ExTMIY* PF4/ExTMIX* PF3/TMOB PF2/TMOA...
Page 40 Pin No. Single-Chip Modes TFP-144 Mode 2, Mode 3 (EXPE = 0) AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 AVCC AVref P60/FTCI/KIN0/TMIX P61/FTOA/KIN1 P62/FTIA/KIN2/TMIY P63/FTIB/KIN3 P64/FTIC/KIN4 P65/FTID/KIN5 P66/FTOB/KIN6/IRQ6 P67/TMOX/KIN7/IRQ7 Rev. 1.00, 05/04, page 6 of 544 Pin Name Flash Memory Programmer Mode...
Page 41 Pin No. Single-Chip Modes TFP-144 Mode 2, Mode 3 (EXPE = 0) P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 PB7/WUE7 PB6/WUE6 PB5/WUE5 PB4/WUE4 PB3/WUE3 PB2/WUE2 PB1/WUE1/LSCI PB0/WUE0/LSMI Pin Name Flash Memory Programmer Mode FA14 FA13 FA12 FA11 FA10 Rev. 1.00, 05/04, page 7 of 544...
Page 42 Pin No. Single-Chip Modes TFP-144 Mode 2, Mode 3 (EXPE = 0) P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37/SERIRQ P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1 P85/IRQ4/RxD1 135 (N) P86/IRQ5/SCK1/SCL1 P40/TMCI0 P41/TMO0 138 (N) P42/TMRI0/SDA1 RESO XTAL EXTAL Note: The (B) in Pin No. means the VCCB drive and the (N) in Pin No. means the NMOS push-pull/open-drain drive.
Page 43: Pin Functions
1.3.3 Pin Functions Table 1.2 Pin Functions Type Symbol Power VCCB Clock XTAL EXTAL φ EXCL Operating mode control System control RESO STBY Interrupt signals IRQ0 to IRQ7 Pin No. TFP-144 Name and Function 1, 86 Input Power supply pin. Connect the pin to the system power supply.
Page 44 Type Symbol 16-bit free- FTCI running timer FTOA (FRT) FTOB FTIA FTIB FTIC FTID 8-bit timer TMO0 (TMR_0, TMO1 TMR_1, TMOX TMR_X, TMOY* TMR_Y, TMOA TMR_A, TMOB TMR_B) ExTMOX* TMCI0 TMCI1 TMRI0 TMRI1 8-bit timer TMIX (TMR_X, TMIY TMR_Y, TMIA TMR_A, TMIB TMR_B)
Page 45 Pin No. Type Symbol TFP-144 Host interface LAD3 to 124 to 121 (LPC) LAD0 LFRAME LRESET LCLK SERIRQ LSCI, LSMI, 119, 120, GA20 CLKRUN LPCPD KIN0 to Keyboard 78 to 85, KIN15 buffer 41 to 37, controller 35 to 33 WUE0 to 120 to 113 WUE7...
Page 46 Type Symbol C bus SCL0 interface (IIC) SCL1 ExSCLA* ExSCLB* SDA0 SDA1 ExSDAA* ExSDAB* I/O ports P17 to P10 P27 to P20 P37 to P30 P47 to P40 P52 to P50 P67 to P60 P77 to P70 P86 to P80 P97 to P90 PA7 to PA0 33 to 35, PB7 to PB0 113 to 120...
Page 47: Section 2 Cpu
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU.
Page 48: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
• Two CPU operating modes Normal mode Advanced mode • Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. •...
Page 49: Differences From H8/300 Cpu
2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. • Expanded address space Normal mode supports the same 64-Kbyte address space as the H8/300 CPU.
Page 50: Cpu Operating Modes
CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode.
Page 51: Figure 2.1 Exception Vector Table (Normal Mode)
H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 H'0007 H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode) (16 bits) (a) Subroutine Branch Note: * Ignored when returning.
Page 52: Advanced Mode
2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers.
Page 53: Figure 2.4 Stack Structure In Advanced Mode
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address.
Page 54: Address Space
Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product.
Page 55: Register Configuration
Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers...
Page 56: General Registers
2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
Page 57: Program Counter (Pc)
SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR)
Page 58: Condition-Code Register (Ccr)
2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Page 59: Initial Register Values
Initial Bit Name Value Undefined R/W 2.4.5 Initial Register Values The program counter (PC) among CPU internal registers is initialized when reset exception handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the interrupt mask (I) bits in CCR and EXR are set to 1.
Page 60: Data Formats
Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 61: Figure 2.9 General Register Data Formats (2)
Data Type Register Number Word data Word data Longword data [Legend] ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB : Least significant bit Figure 2.9 General Register Data Formats (2) Data Image Rev.
Page 62: Memory Data Formats
2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 63: Instruction Set
Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer POP* , PUSH* LDM* , STM* MOVFPE* Arithmetic ADD, SUB, CMP, NEG operations ADDX, SUBX, DAA, DAS INC, DEC...
Page 64: Table Of Instructions Classified By Function
2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination)* General register (source)* General register* General register (32-bit register) (EAd)
Page 65: Table 2.3 Data Transfer Instructions
Table 2.3 Data Transfer Instructions Instruction Size* B/W/L MOVFPE MOVTPE PUSH LDM* STM* Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer.
Page 66: Table 2.4 Arithmetic Operations Instructions (1)
Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* B/W/L ADDX SUBX B/W/L ADDS SUBS MULXU MULXS DIVXU Note: Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00, 05/04, page 32 of 544 Function Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register.
Page 67: Table 2.4 Arithmetic Operations Instructions (2)
Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* DIVXS B/W/L B/W/L EXTU EXTS TAS* Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. Function Rd ÷...
Page 68: Table 2.5 Logic Operations Instructions
Table 2.5 Logic Operations Instructions Instruction Size* B/W/L B/W/L B/W/L B/W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Shift Instructions Instruction Size* SHAL B/W/L SHAR SHLL B/W/L SHLR ROTL B/W/L ROTR ROTXL B/W/L ROTXR...
Page 69: Table 2.7 Bit Manipulation Instructions (1)
Table 2.7 Bit Manipulation Instructions (1) Instruction Size* BSET BCLR BNOT BTST BAND BIAND BIOR Note: Size refers to the operand size. B: Byte Function 1 → (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 70: Table 2.7 Bit Manipulation Instructions (2)
Table 2.7 Bit Manipulation Instructions (2) Instruction Size* BXOR BIXOR BILD BIST Note: Size refers to the operand size. B: Byte Rev. 1.00, 05/04, page 36 of 544 Function C ⊕ (<bit-No.> of <EAd>) → C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
Page 71: Table 2.8 Branch Instructions
Table 2.8 Branch Instructions Instruction Size — — — — — Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description BRA (BT) Always (true) BRN (BF) Never (false) High Low or same BCC (BHS) Carry clear...
Page 72: Table 2.9 System Control Instructions
Table 2.9 System Control Instructions Instruction Size* TRAPA — — SLEEP — ANDC XORC — Note: Size refers to the operand size. B: Byte W: Word Table 2.10 Block Data Transfer Instructions Instruction Size EEPMOV.B — EEPMOV.W — Rev. 1.00, 05/04, page 38 of 544 Function Starts trap-instruction exception handling.
Page 73: Basic Instruction Formats
2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. •...
Page 74: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes.
Page 75: Register Indirect With Displacement-@(D:16, Ern) Or @(D:32, Ern)
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand.
Page 76: Immediate-#Xx:8, #Xx:16, Or #Xx:32
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction code can be used directly as an operand. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their instruction codes.
Page 77: Memory Indirect-@@Aa:8
2.7.8 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
Page 78: Effective Address Calculation
2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Register direct (Rn) Register indirect (@ERn)
Page 79: Table 2.13 Effective Address Calculation (2)
Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents Memory contents Rev. 1.00, 05/04, page 45 of 544...
Page 80: Processing States
Processing States The H8S/2000 CPU has four main processing states: the reset state, exception handling state, program execution state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state.
Page 81: Figure 2.13 State Transitions
End of exception handling Exception-handling state RES = high Reset state* From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition can also be made to the reset state when the watchdog timer overflows. From any state, a transition to hardware standby mode occurs when STBY goes low.
Page 82: Usage Notes
When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. When the TAS instruction is used as a user-defined intrinsic function, use registers ER0, ER1, ER4 and ER5.
Page 83: Eepmov Instruction
2.9.4 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. R5 + R4L 2. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution).
Page 84 Rev. 1.00, 05/04, page 50 of 544...
Page 85: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes MCU Operating Mode Selection This LSI has two operating modes (modes 2 and 3). The operating mode is determined by the setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU operating mode selection. Table 3.1 lists the MCU operating modes.
Page 86: Register Descriptions
Register Descriptions The following registers are related to the operating mode. Mode control register (MDCR) System control register (SYSCR) Serial timer control register (STCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to monitor the current operating mode. Initial Bit Name Value EXPE —...
Page 87: System Control Register (Syscr)
3.2.2 System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, pin location selection, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space. Initial Bit Name Value...
Page 88 Initial Bit Name Value RAME Rev. 1.00, 05/04, page 54 of 544 Description Host Interface Enable Controls CPU access to the keyboard matrix interrupt, input pull-up MOS control registers (KMIMR, KMPCR, and KMIMRA), and the 8-bit timer (TMR_X and TMR_Y) registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, and TCORB_X, TCONRI, and TCONRS).
Page 89: Serial Timer Control Register (Stcr)
3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Initial Bit Name Value IICS IICX1 IICX0 IICE Description C Extra Buffer Select Specifies bits 7 to 4 of port A as output buffers similar to SLC and SDA.
Page 90: Operating Mode Descriptions
Initial Bit Name Value FLSHE — ICKS1 ICKS0 Operating Mode Descriptions 3.3.1 Mode 2 The CPU can access a 16-Mbyte address space in advanced single-chip mode. The on-chip ROM is enabled. 3.3.2 Mode 3 The CPU can access a 64-Kbyte address space in normal single-chip mode. The on-chip ROM is enabled.
Page 91: Address Map
H'000000 H'00FFFF H'01FFFF H'FFE080 H'FFE880 H'FFEFFF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Figure 3.1 Address Map for H8S/2111B-B H'0000 On-chip ROM Reserved area H'DFFF H'E080 Reserved area H'E880 On-chip RAM H'EFFF H'F800 Internal I/O registers 3 H'FE4F H'FE50...
Page 92: Figure 3.2 Address Map For H8S/2111B-C
H'01FFFF H'FFE080 H'FFE480 H'FFEFFF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Figure 3.2 Address Map for H8S/2111B-C Rev. 1.00, 05/04, page 58 of 544 H'0000 On-chip ROM Reserved area H'DFFF H'E080 Reserved area H'E480 On-chip RAM H'EFFF H'F800 Internal I/O...
Page 93: Section 4 Exception Handling
Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 94: Exception Sources And Exception Vector Table
Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Exception Source Reset Reserved for system use Direct transition External interrupt (NMI) Trap instruction (four sources)
Page 95: Reset
Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on.
Page 96: Interrupts After Reset
4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Page 97: Interrupt Exception Handling
Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ7 to IRQ0, KIN15 to KIN0, and WUE7 to WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority.
Page 98: Stack Status After Exception Handling
Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode Advanced mode CCR* (24 bits) (16 bits) Note: Ignored on return. Figure 4.2 Stack Status after Exception Handling Rev.
Page 99: Usage Note
Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP)
Page 100 Rev. 1.00, 05/04, page 66 of 544...
Page 101: Section 5 Interrupt Controller
Section 5 Interrupt Controller Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI and address break.
Page 102: Input/Output Pins
SYSCR NMIEG NMI input IRQ input KIN input WUE input Internal interrupt request WOVI0 to IBFI3 Interrupt controller [Legend] Interrupt control register ICR: IRQ sense control register ISCR: IRQ enable register IER: IRQ status register ISR: Figure 5.1 Block Diagram of Interrupt Controller Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller.
Page 103: Register Descriptions
Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR). • Interrupt control registers A to C (ICRA to ICRC) • Address break control register (ABRKCR) •...
Page 104: Address Break Control Register (Abrkcr)
Table 5.2 Correspondence between Interrupt Source and ICR Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0 [Legend] A to C : Reserved. The write value should always be 0. 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an address break is requested.
Page 105: Break Address Registers A To C (Bara To Barc)
5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared.
Page 106: Irq Sense Control Registers (Iscrh, Iscrl)
5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0. • ISCRH Initial Bit Name Value IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA • ISCRL Initial Bit Name Value IRQ3SCB...
Page 107: Irq Enable Register (Ier)
5.3.5 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0. Initial Bit Name Value IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E 5.3.6 IRQ Status Register (ISR) The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests. Initial Bit Name Value...
Page 108 • KMIMRA Initial Bit Name Value KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 • KMIMR Initial Bit Name Value KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 • WUEMRB Initial Bit Name Value WUEMR7 WUEMR6 WUEMR5 WUEMR4 WUEMR3 WUEMR2 WUEMR1 WUEMR0 Rev.
Page 109: Figure 5.2 Relationship Between Interrupts Irq7 And Irq6, Interrupts Kin15 To Kin0, Interrupts Wue7 To Wue0, And Registers Kmimr, Kmimra, And Wuemrb
Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0, interrupts WUE7 to WUE0, and registers KMIMRA, KMIMR, and WUEMRB. KMIMR0 (initial value 1) P60/KIN0 KMIMR5 (initial value 1) P65/KIN5 KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7 KMIMR8 (initial value 1) PA0/KIN8...
Page 110: Interrupt Sources
Interrupt Sources 5.4.1 External Interrupts There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WUE7 to WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6 , and IRQ2 to IRQ0 can be used to restore this LSI from software standby mode.
Page 111: Internal Interrupts
When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and WUEMR7 to WUEMR0 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the IRQ7 pin will be ignored. Since interrupt request flags IRQ7F to IRQ0F are set each time the setting condition is satisfied, regardless of the IER setting, refer to a needed flag only.
Page 112: Interrupt Exception Handling Vector Table
Interrupt Exception Handling Vector Table Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned.
Page 113 Origin of Interrupt Name Source TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match A) OVI0 (Overflow) Reserved for system use TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use TMR_X, CMIAY (Compare match A) TMR_Y CMIBY (Compare match B) OVIY (Overflow)
Page 114: Interrupt Control Modes And Interrupt Operation
Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR.
Page 115: Figure 5.4 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 0
7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. An interrupt with interrupt control level 1? IRQ0 Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Program excution state...
Page 116: Interrupt Control Mode 1
5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. •...
Page 117 Figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority).
Page 118: Figure 5.6 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 1
An interrupt with interrupt control level 1? IRQ0 Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance Rev. 1.00, 05/04, page 84 of 544 Program excution state Interrupt generated? IRQ0 IRQ1 IFBFI3 I = 0 UI = 0 Save PC and CCR 1, UI Read vector address Branch to interrupt handling routine...
Page 119: Interrupt Exception Handling Sequence
5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5.7 Interrupt Exception Handling Rev.
Page 120: Interrupt Response Times
5.6.4 Interrupt Response Times Table 5.5 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.5 are explained in table 5.6. Table 5.5 Interrupt Response Times No.
Page 121: Address Break
Address Break 5.7.1 Features This LSI can determine the specific address prefetch by the CPU to generate an address break interrupt by setting ABRKCR and BAR. If an address break interrupt is generated, the address break interrupt exception handling is performed. With this function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program.
Page 122: Operation
5.7.3 Operation If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address break interrupt can be generated. This address break function generates an interrupt request to the interrupt controller at prefetch, and determines the priority by the interrupt controller. When an interrupt is accepted, an interrupt exception handling is activated after the current instruction has been completed.
Page 123: Figure 5.9 Address Break Timing Example
Figure 5.9 shows an example of address timing. (1) When a break address specified instruction is executed for one state in the program area and on-chip memory Instruction Instruction fetch fetch φ Address bus H'0310 H'0312 H'0314 H'0316 execution Break request signal H'0310 NOP H'0312 NOP...
Page 124: Usage Notes
Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 125: Instructions That Disable Interrupts
5.8.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 126 Rev. 1.00, 05/04, page 92 of 544...
Page 127: Section 6 Bus Controller (Bsc)
Section 6 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an on-chip bus controller (BSC). Considering the software compatibility with similar products, you must be careful to set appropriate values to the control registers for the bus controller. Register Descriptions The bus controller has the following registers.
Page 128: Wait State Control Register (Wscr)
6.1.2 Wait State Control Register (WSCR) Initial Bit Name Value — — WMS1 WMS0 Rev. 1.00, 05/04, page 94 of 544 Description Reserved The initial value should not be changed. Bus Width Control The initial value should not be changed. Access State Control The initial value should not be changed.
Page 129: Section 7 I/O Ports
Section 7 I/O Ports This LSI has fifteen I/O ports (ports 1 to 6, 8, 9, and A to G), and one input-only port (port 7). Table 7.1 is a summary of the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port) and data registers (DR, ODR) that store output data.
Page 130: Table 7.1 Port Functions
Table 7.1 Port Functions Port Description Port 1 General I/O port also functioning as PWM output pins Port 2 General I/O port Port 3 General I/O port also functioning as LPC input/output pins Port 4 General I/O port also functioning as TMR_0 and TMR_1 input/output, and IIC_1 input/output pins Port 5...
Page 131 Port Description Port 6 General I/O port also functioning as interrupt input, FRT input/output, TMR_X and TMR_Y input/output, and key- sense interrupt input Port 7 General input port also functioning as A/D converter analog input Port 8 General I/O port also functioning as interrupt input, SCI_1 input/output, LPC input/output, and...
Page 132 Port Description Port A General I/O port also functioning as key-sense interrupt input and keyboard buffer controller input/output pins Port B General I/O port also functioning as wakeup event interrupt input and LPC input/output pins Port C General I/O port Port D General I/O port Rev.
Page 133 Port Description Port E General I/O port Port F General I/O port also functioning as TMR_X, TMR_Y, TMR_A, and TMR_B input/output pins Port G General I/O port also functioning as IIC_1 and IIC_0 input/output pins Note: The program development tool (emulator) does not support this function. Mode 2and Mode 3 PF7/TMOY* PF6/ExTMOX*...
Page 134: Port 1
Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as PWM output pins. Port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 pull-up MOS control register (P1PCR) 7.1.1 Port 1 Data Direction Register (P1DDR) P1DDR specifies input or output for the pins of port 1 on a bit-by-bit basis.
Page 135: Port 1 Pull-Up Mos Control Register (P1Pcr)
7.1.3 Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the on/off state of the port 1 on-chip input pull-up MOSs. Initial Bit Name Value P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR 7.1.4 Pin Functions • P17/PW7 to P10/PW0 The pin function is switched as shown below according to the combination of the OEn bit in PWOERA of PWM and the P1nDDR bit.
Page 136: Port 1 Input Pull-Up Mos
7.1.5 Port 1 Input Pull-Up MOS Port 1 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 7.2 summarizes the input pull-up MOS states. Table 7.2 Input Pull-Up MOS States (Port 1) Reset...
Page 137: Port 2 Data Register (P2Dr))
7.2.2 Port 2 Data Register (P2DR)) P2DR stores output data for port 2. Initial Bit Name Value P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR 7.2.3 Port 2 Pull-Up MOS Control Register (P2PCR) P2PCR controls the port 2 on-chip input pull-up MOSs. Initial Bit Name Value...
Page 138: Port 2 Input Pull-Up Mos
7.2.5 Port 2 Input Pull-Up MOS Port 2 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 7.3 summarizes the input pull-up MOS states. Table 7.3 Input Pull-Up MOS States (Port 2) Hardware...
Page 139: Port 3 Data Register (P3Dr)
7.3.2 Port 3 Data Register (P3DR) P3DR stores output data of port 3. Initial Bit Name Value P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR 7.3.3 Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the port 3 on-chip input pull-up MOSs on a bit-by-bit basis. Initial Bit Name Value...
Page 140: Pin Functions
7.3.4 Pin Functions • P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 The pin function is switched as shown below according to the combination of the LPC3E to LPC1E bits in HICR0 of the host interface (LPC) and the P3nDDR bit. LPCmE P3nDDR Pin Function...
Page 141: Port 4
Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as TMR_0 and TMR_1 I/O pins, and the IIC_1 I/O pin. The output type of P42 is NMOS push-pull output. The output type of SDA1 is NMOS open-drain output.
Page 142: Pin Functions
7.4.3 Pin Functions • P47 The pin function is switched as shown below according to the combination of the P47DDR bit. P47DDR Pin Function • P46 The pin function is switched as shown below according to the combination of the P46DDR bit. P46DDR Pin Function •...
Page 143 • P43/TMCI1 The pin function is switched as shown below according to the state of the P43DDR bit. P43DDR Pin Function Note: When the external clock is selected by the bits CKS2 to CKS0 in TCR1 of TMR_1, this pin is used as the TMCI1 input pin. •...
Page 144: Port 5
Port 5 Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI_1 extended I/O pins, and the IIC_0 I/O pin. P52 and ExSCK1 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output. Port 5 has the following registers. •...
Page 145: Pin Functions
7.5.3 Pin Functions • P52/ExSCK1*/SCL0 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, the CKE0 and CKE1 bits in SCR, the SPS1 bit* of IIC_0, the IIC0AS and the IIC0BS bits in PGCTL* P52ICE = ICE •...
Page 146: Port 6
• P50/ExTxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1, the SPS1 bit* in SPSR, and the P50DDR bit. SPS1* P50DDR Pin Function P50 input pin Note: The program development tool (emulator) does not support this function. Port 6 Port 6 is an 8-bit I/O port.
Page 147: Port 6 Data Register (P6Dr)
7.6.2 Port 6 Data Register (P6DR) P6DR stores output data for port 6. Initial Bit Name Value P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR 7.6.3 Port 6 Pull-Up MOS Control Register (KMPCR) KMPCR controls the port 6 on-chip input pull-up MOSs on a bit-by-bit basis. Initial Bit Name Value...
Page 148: System Control Register 2 (Syscr2)
7.6.4 System Control Register 2 (SYSCR2) SYSCR2 is not available in this LSI although originally designed to control the port 6 operations. Initial Bit Name Value 7 to 0 — All 0 7.6.5 Pin Functions • P67/TMOX/KIN7/IRQ7 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_X, the IOSX bit* IOSX* OS3 to OS0...
Page 149 • P66/FTOB/KIN6/IRQ6 The pin function is switched as shown below according to the combination of the OEB bit in TOCR of the FRT and the P66DDR bit. P66DDR Pin Function P66 input pin This pin is used as the IRQ6 input pin when bit IRQ6E is set to 1 in IER while the Note: KMIMR6 bit in KMIMR is 0.
Page 150: Port 6 Input Pull-Up Mos
• P61/FTOA/KIN1 The pin function is switched as shown below according to the combination of the OEA bit in TOCR of the FRT, and the P61DDR bit. P61DDR Pin Function P61 input pin This pin can always be used as the KIN1 input pin. Note: * •...
Page 151: Port 7
Port 7 Port 7 is an 8-bit input only port. Port 7 pins also function as the A/D converter analog input pins. Port 7 has the following register. • Port 7 input data register (P7PIN) 7.7.1 Port 7 Input Data Register (P7PIN) P7PIN reflects the pin states of port 7.
Page 152: Port 8
Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI_1 I/O pins, the IIC_1 I/O pins, LPC I/O pins, and interrupt input pins. The output type of P86 and SCK1 is NMOS push-pull output. The output type of SCL1 is NMOS open-drain output and direct bus driving is enabled.
Page 153: Pin Functions
7.8.3 Pin Functions • P86/IRQ5/SCK1/SCL1 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, the CKE0 and CKE1 bits in SCR, the SPS1 bit* of IIC_1, the IIC1AS and the IIC1BS bits in PGCTL* P86ICE = ICE •...
Page 154 • P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1, the SPS1 bit* SPS1* P84DDR Pin Function P84 input Notes: 1. When the IRQ3E bit in IER is set to 1, this pin is used as the IRQ3 input pin. 2.
Page 155 • P81/GA20 The pin function is switched as shown below according to the combination of the FGA20E bit in HICR0 and the P81DDR bit. FGA20E P81DDR Pin Function P81 input pin Note: * When bit FGA20E is set to 1 in HICR0, the P81DDR bit should be cleared to 0. •...
Page 156: Port 9
Port 9 Port 9 is an 8-bit I/O port. Port 9 pins also function as the interrupt input pins, IIC_0 I/O pin, subclock input pin, and system clock (φ) output pin. P97 is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. Port 9 has the following registers.
Page 157: Pin Functions
7.9.3 Pin Functions • P97/SDA0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0, the IIC0AS and the IIC0BS bits in PGCTL*, and the P97DDR bit. P97ICE = ICE •...
Page 158 • P92/IRQ0 The pin function is switched as shown below according to the state of the P92DDR bit. P92DDR Pin Function When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin. Note: •...
Page 159: Port A
7.10 Port A Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins, and key-sense interrupt input pins. Port A input/output operates by VccB power independent from the Vcc power. Up to 5 V can be applied to port A pins if VccB power is 5 V. Port A has the following registers.
Page 160: Port A Input Data Register (Papin)
7.10.3 Port A Input Data Register (PAPIN) PAPIN indicates the port A state. Bit Name Initial Value R/W PA7PIN Undefined* PA6PIN Undefined* PA5PIN Undefined* PA4PIN Undefined* PA3PIN Undefined* PA2PIN Undefined* PA1PIN Undefined* PA0PIN Undefined* Note: The initial value is determined according to the PA7 to PA0 pin states. 7.10.4 Pin Functions •...
Page 161 • PA5/KIN13/PS2BD The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_1 of the keyboard buffer controller, and the PA5DDR bit. KBIOE PA5DDR Pin Function PA5 input pin Note: When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability.
Page 162: Port A Input Pull-Up Mos
• PA2/KIN10/PS2AC The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_0 of the keyboard buffer controller, and the PA2DDR bit. KBIOE PA2DDR Pin Function PA2 input pin Note: * When the KBIOE bit is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability.
Page 163: Port B
7.11 Port B Port B is an 8-bit I/O port. Port B pins also have LPC input/output pins, and wakeup event interrupt input pins function. Port B has the following registers. • Port B data direction register (PBDDR) • Port B output data register (PBODR) •...
Page 164: Port B Input Data Register (Pbpin)
7.11.3 Port B Input Data Register (PBPIN) PBPIN indicates the port B state. Initial Bit Name Value PB7PIN Undefined* R PB6PIN Undefined* R PB5PIN Undefined* R PB4PIN Undefined* R PB3PIN Undefined* R PB2PIN Undefined* R PB1PIN Undefined* R PB0PIN Undefined* R Note: The initial value is determined according to the PB7 to PB0 pin states.
Page 165: Port B Input Pull-Up Mos
• PB0/WUE0/LSMI The pin function is switched as shown below according to the combination of the LSMIE bit in HICR0 of the host interface (LPC) and the PB0DDR bit. LSMIE PB0DDR Pin Function PB0 input pin Notes: 1. When the LSMIE bit in HICR0 is set to 1, the PB0DDR bit should be cleared to 0. 2.
Page 166: Ports C, D
7.12 Ports C, D Port C and port D are two sets of 8-bit I/O ports. Port C and port D have the following registers. • Port C data direction register (PCDDR) • Port C output data register (PCODR) • Port C input data register (PCPIN) •...
Page 167: Port C And Port D Output Data Registers (Pcodr, Pdodr)
7.12.2 Port C and Port D Output Data Registers (PCODR, PDODR) PCODR and PDODR store output data for the pins on ports C and D. Initial Bit Name Value PC7ODR 0 PC6ODR 0 PC5ODR 0 PC4ODR 0 PC3ODR 0 PC2ODR 0 PC1ODR 0 PC0ODR 0 Initial...
Page 168: Port C And Port D Nch-Od Control Register (Pcnocr, Pdnocr)
Initial Bit Name Value PD7PIN Undefined* R PD6PIN Undefined* R PD5PIN Undefined* R PD4PIN Undefined* R PD3PIN Undefined* R PD2PIN Undefined* R PD1PIN Undefined* R PD0PIN Undefined* R Note: The initial value is determined according to the PD7 to PD0 pin states. 7.12.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR) PCNOCR and PDNOCR specify the output driver type for pins on ports C and D which are...
Page 169: Pin Functions
7.12.5 Pin Functions NOCR N-ch. driver P-ch. driver Input pull-up Pin function 7.12.6 Input Pull-Up MOS in Ports C and D Port C and port D have an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be switched on or off on a bit-by-bit basis. Table 7.8 is a summary of the input pull-up MOS states.
Page 170: Ports E, F
7.13 Ports E, F Ports E and F are two sets of 8-bit I/O ports. Port F also functions as I/O pins for TMR_X*, TMR_Y*, TMR_A, and TMR_B. Ports E and F have the following registers. • Port E data direction register (PEDDR) •...
Page 171: Port E And Port F Output Data Registers (Peodr, Pfodr)
7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR) PEODR and PFODR store output data for the pins on ports E and F. Initial Bit Name Value PE7ODR PE6ODR PE5ODR PE4ODR PE3ODR PE2ODR PE1ODR PE0ODR Initial Bit Name Value PF7ODR PF6ODR...
Page 172: Port E And Port F Input Data Registers (Pepin, Pfpin)
7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN) Reading PEPIN and PFPIN always returns the pin states. Initial Bit Name Value PE7PIN Undefined* R PE6PIN Undefined* R PE5PIN Undefined* R PE4PIN Undefined* R PE3PIN Undefined* R PE2PIN Undefined* R PE1PIN Undefined* R...
Page 173 • PF6/ExTMOX The pin function is switched as shown below according to the combination of the IOSX bit* in TCRXY of TMR_X, the OS3 to OS0 bits in TCSR_X, and the PF6DDR bit. IOSX* OS3 to OS0 PF6DDR Pin Function input pin Notes: * The program development tool (emulator) does not support this function.
Page 174: Port E And Port F Nch-Od Control Register (Penocr, Pfnocr)
• PF2/TMOA The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR_A of TMR_A and the PF2DDR bit. OS3 to OS0 PF3DDR Pin Function PF2 input pin • PF1/TMIB The pin function is switched as shown below according to the state of the PF1DDR bit. PF1DDR Pin Function Note:...
Page 175: Pin Functions
Initial Bit Name Value PF7NOCR PF6NOCR PF5NOCR PF4NOCR PF3NOCR PF2NOCR PF1NOCR PF0NOCR 7.13.6 Pin Functions NOCR N-ch. driver P-ch. driver Input pull-up Pin function Note: Includes when set as the timer output pin. 7.13.7 Input Pull-Up MOS in Ports E and F Port E and port F have an on-chip input pull-up MOS function that can be controlled by software.
Page 176: Port G
7.14 Port G Port G is an 8-bit I/O port. Port G pins also function as IIC_0 and IIC_1 I/O pins. The output type of port G is NMOS push-pull output. The output type of ExSCLB*, ExSDAB*, ExSCLA*, and ExSDAA* is NMOS open-drain output and the pins can directly drive the bus. Port G has the following registers.
Page 177: Port G Output Data Register
7.14.2 Port G Output Data Register (PGODR) PGODR stores output data for the pins on port G. Initial Bit Name Value PG7ODR PG6ODR PG5ODR PG4ODR PG3ODR PG2ODR PG1ODR PG0ODR 7.14.3 Port G Input Data Register (PGPIN) Reading PGPIN always returns the pin states. Initial Bit Name Value...
Page 178: Pin Functions
7.14.4 Pin Functions • PG7/ExSCLB The pin function is switched as shown below according to the combination of the IIC1BS and the IIC0BS bits in PGCTL of the IIC* and the PG7DDR bit. IIC1BS and IIC0BS* PG7DDR Pin Function PG7 input pin Note: The program development tool (emulator) does not support this function.
Page 179: Port G Nch-Od Control Register
• PG3, PG2, PG1, PG0 The pin function is switched as shown below according to the state of the PGnDDR bit. PGnDDR Pin Function [Legend] n = 3 to 0 7.14.5 Port G Nch-OD Control Register (PGNOCR) PGNOCR specifies the output driver type for pins on port G which are configured as outputs on a bit-by-bit basis.
Page 180 Rev. 1.00, 05/04, page 146 of 544...
Page 181: Section 8 8-Bit Pwm Timer (Pwm)
Section 8 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer with eight outputs. Eight output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division. Connecting a low pass filter externally to the LSI enables the PWM to function as an 8-bit D/A converter.
Page 182: Input/Output Pins
Input/Output Pins Table 8.1 shows the PWM output pins. Table 8.1 Pin Configuration Name PWM output 7 to 0 Register Descriptions The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see section 3.2.3, Serial Timer Control Register (STCR).
Page 183: Pwm Register Select (Pwsl)
8.3.1 PWM Register Select (PWSL) PWSL is used to select the input clock and the PWM data register. Bit Name Initial Value PWCKE PWCKS — — [Legend] Don't care. Description PWM Clock Enable PWM Clock Select These bits, together with bits PWCKC, PWCKB and PWCKA in PCSR, select the internal clock input to TCNT in the PWM.
Page 184: Table 8.2 Internal Clock Selection
Table 8.2 Internal Clock Selection PWSL PWCKE PWCKS PWCKC PWCKB PWCKA — — — Note: The program development tool (emulator) does not support this function. Resolution, PWM Conversion Period, and Carrier Frequency when φ = 10 MHz Table 8.3 Internal Clock Frequency Resolution φ...
Page 185: Pwm Data Registers 7 To 0 (Pwdr7 To Pwd0)
8.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWD0) PWDR are 8-bit readable/writable registers. The PWM has eight PWM data registers. Each PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional pulses.
Page 186: Pwm Output Enable Register A (Pwoera)
8.3.4 PWM Output Enable Register A (PWOERA) PWOERA switches between PWM output and port output. Initial Name Value [Legend] Don't care Note: n = 7 to 0 To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set to port output.
Page 187: Operation
Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 8.4 shows the duty cycles of the basic pulse. Table 8.4 Duty Cycle of Basic Pulse Upper 4 Bits B ' 0 0 0 0 B ' 0 0 0 1...
Page 188: Figure 8.2 Example Of Additional Pulse Timing (When Upper 4 Bits Of Pwdr = B'1000)
The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the rising edge of a basic pulse. When the upper four bits of PWDR are B'0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same.
Page 189: Pwm Setting Example
8.4.1 PWM Setting Example PWDR setting example H'7F H'80 H'81 H'82 : Pulse added Combination of the basic pulse and added pulse outputs 0/256 to 255/256 of dudty cycle as low ripple wave form. 8.4.2 Diagram of PWM Used as D/A Converter Figure 8.4 shows the diagram example when using the PWM pulse as the D/A converter.
Page 190: Usage Notes
Usage Notes 8.5.1 Module Stop Mode Setting PWM operation can be enabled or disabled by the module stop control register. In the initial state, PWM operation is disabled. Access to PWM registers is enabled when module stop mode is cancelled. For details, see section 20, Power-Down Modes. Rev.
Page 191: Section 9 16-Bit Free-Running Timer (Frt)
Section 9 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16- bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods. Features •...
Page 192: Figure 9.1 Block Diagram Of 16-Bit Free-Running Timer
Figure 9.1 shows a block diagram of the FRT. External clock Internal clock FTCI Clock selector FTOA FTOB FTIA FTIB FTIC FTID Control logic Compare-match M [Legend] OCRA, OCRB : Output compare register A, B (16-bit) OCRAR,OCRAF : Output compare register AR, AF (16-bit) OCRDM : Output compare register DM (16-bit) : Free-running counter (16-bit)
Page 193: Input/Output Pins
Input/Output Pins Table 9.1 lists the FRT input and output pins. Table 9.1 Pin Configuration Name Counter clock input pin Output compare A output pin Output compare B output pin Input capture A input pin Input capture B input pin Input capture C input pin Input capture D input pin Register Descriptions...
Page 194: Free-Running Counter (Frc)
9.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units;...
Page 195: Output Compare Registers Ar And Af (Ocrar, Ocraf)
9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA.
Page 196: Timer Interrupt Enable Register (Tier)
9.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Initial Bit Name Value ICIAE ICIBE ICICE ICIDE OCIAE Rev. 1.00, 05/04, page 162 of 544 Description Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
Page 197: Timer Control/Status Register (Tcsr)
Initial Bit Name Value OCIBE OVIE — 9.3.7 Timer Control/Status Register (TCSR) TCSR is used for counter clear selection and control of interrupt request signals. Initial Bit Name Value ICFA Description Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Page 198 Initial Bit Name Value ICFB ICFC ICFD Rev. 1.00, 05/04, page 164 of 544 Description R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB.
Page 199 Initial Bit Name Value OCFA OCFB CCLRA Note: Only 0 can be written to clear the flag. Description R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. Only 0 can be written to this bit to clear the flag.
Page 200: Timer Control Register (Tcr)
9.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Initial Bit Name Value IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB Rev. 1.00, 05/04, page 166 of 544 Description Input Edge Select A Selects the rising or falling edge of the input capture A...
Page 201: Timer Output Compare Control Register (Tocr)
Initial Bit Name Value CKS1 CKS0 9.3.9 Timer Output Compare Control Register (TOCR) TOCR enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, controls the ICRD and OCRA operating modes, and switches access to input capture registers A, B, and C.
Page 202 Initial Bit Name Value OCRS OLVLA OLVLB Rev. 1.00, 05/04, page 168 of 544 Description Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected.
Page 203: Operation
Operation 9.4.1 Pulse Output Figure 9.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software. H'FFFF OCRA OCRB...
Page 204: Operation Timing
Operation Timing 9.5.1 FRC Increment Timing Figure 9.3 shows the FRC increment timing with an internal clock source. Figure 9.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (φ).
Page 205: Output Compare Output Timing
9.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure 9.5 shows the timing of this operation for compare-match A.
Page 206: Input Capture Input Timing
9.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 9.7 shows the usual input capture timing when the rising edge is selected.
Page 207: Buffered Input Capture Input Timing
9.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 9.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
Page 208: Timing Of Input Capture Flag (Icf) Setting
9.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB, ICRC, or ICRD).
Page 209: Timing Of Frc Overflow Flag Setting
9.5.8 Timing of FRC Overflow Flag Setting The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 9.13 shows the timing of setting the OVF flag. φ Overflow signal Figure 9.13 Timing of Overflow Flag (OVF) Setting 9.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are...
Page 210: Mask Signal Generation Timing
9.5.10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture signal is generated. The mask signal is set by the input capture signal.
Page 211: Interrupt Sources
Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 9.2 lists the sources and priorities of these interrupts. Table 9.2 FRT Interrupt Sources Interrupt...
Page 212: Conflict Between Frc Write And Increment
9.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 9.18 shows the timing for this type of conflict. φ...
Page 213: Figure 9.19 Conflict Between Ocr Write And Compare-Match (When Automatic Addition Function Is Not Used)
φ Address Internal write signal Compare-match signal Figure 9.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Not Used) Address Internal write signal OCRAR (OCRAF) Compare-match signal Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function is Used) Write cycle of OCR OCR address N + 1...
Page 214: Switching Of Internal Clock And Frc Operation
9.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 9.3. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (φ).
Page 215: Module Stop Mode Setting
Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to low Switching from high to high Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. 9.7.5 Module Stop Mode Setting FRT operation can be enabled or disabled using the module stop control register.
Page 216 Rev. 1.00, 05/04, page 182 of 544...
Page 217: Section 10 8-Bit Timer (Tmr)
Section 10 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, TMR_X, TMR_B, and TMR_A) with six channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
Page 218: Table 10.1 Tmr Function
Table 10.1 TMR Function Item TMR_0 φ/2 Count clock φ/8 φ/32 φ/64 φ/256 φ/1024 I/O pins TMO0 TMCI0 TMRI0 Counter clear function Compare-match A Compare-match B External reset Pulse output Compare-match 0 output output 1 output Toggle output Cascaded connection 16-bit count mode ...
Page 219 Figures 10.1 to 10.3 show block diagrams of 8-bit timers. Internal clock External clock sources sources TMCI0 TMCI1 Clock select TMO0 TMRI0 Control logic TMO1 TMRI1 [Legend] Time constant register A_0 TCORA_0: Time constant register B_0 TCORB_0: Timer counter_0 TCNT_0: Timer control/status register_0 TCSR_0: Timer control register_0...
Page 220: Figure 10.2 Block Diagram Of 8-Bit Timer (Tmr_Y And Tmr_X)
External clock Internal clock sources sources ExTMCIY*/TMCIY ExTMCIX*/TMCIX Clock select TMOY* ExTMRIY*/TMRIY Control logic ExTMOX*/TMOX ExTMRIX*/TMRIX [Legend] TCORA_Y: Time constant register A_Y TCORB_Y: Time constant register B_Y TCNT_Y: Timer counter_Y TCSR_Y: Timer control/status register_Y TCR_Y: Timer control register_Y TISR: Timer input select register Note: The program development tool (emulator) does not support this function.
Page 221: Figure 10.3 Block Diagram Of 8-Bit Timer (Tmr_B And Tmr_A)
External clock Internal clock sources sources TMR_A TMCIB φ, φ/2, φ/4, φ/2048, φ/4096, φ/8192 TMCIA TMR_B φ/4, φ/256, φ/2048, φ/4096, φ/8192, φ/16384 Clock A Clock B Clock select Compare-match AA Compare-match AB Overflow A Overflow B Compare- match BA TMOB Compare-match BB TMRIB Control...
Page 222: Input/Output Pins
10.2 Input/Output Pins Table 10.2 summarizes the input and output pins of the TMR. Table 10.2 Pin Configuration Channel Name TMR_0 Timer output Timer clock input TMCI0 Timer reset input TMRI0 TMR_1 Timer output Timer clock input TMCI1 Timer reset input TMRI1 TMR_Y Timer clock/ reset input...
Page 223: Register Descriptions
10.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). TMR_0 Timer counter_0 (TCNT_0) Time constant register A_0 (TCORA_0) Time constant register B_0 (TCORB_0) Timer control register_0 (TCR_0) Timer control/status register_0 (TCSR_0) TMR_1 Timer counter_1 (TCNT_1)
Page 224 For both TMR_Y and TMR_X Timer XY control register (TCRXY) TMR_B Timer counter_B (TCNT_B) Time constant register A_B (TCORA_B) Time constant register B_B (TCORB_B) Timer control register_B (TCR_B) Timer control/status register_B (TCSR_B) Timer input select register_B (TISR_B) TMR_A Timer counter_A (TCNT_A) Time constant register A_A (TCORA_A) Time constant register B_A (TCORB_A) Timer control register_A (TCR_A)
Page 225: Timer Counter (Tcnt)
10.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16- bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, compare- match A signal or compare-match B signal.
Page 226: Timer Control Register (Tcr)
10.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. TCR_Y can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 1. TCR_X can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 0.
Page 227: Table 10.3 Clock Input To Tcnt And Count Condition (1)
Table 10.3 Clock Input to TCNT and Count Condition (1) Channel CKS2 CKS1 CKS0 TMR_0 TMR_1 Common 1 Note: If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated.
Page 228: Table 10.3 Clock Input To Tcnt And Count Condition (2)
Table 10.3 Clock Input to TCNT and Count Condition (2) Channel CKS2 CKS1 CKS0 TMR_Y TMR_X Notes: 1. If the TMR_Y clock input is set as the TCNT_X overflow signal and the TMR_X clock input is set as the TCNT_Y compare-match signal simultaneously, a count-up clock cannot be generated.
Page 229: Table 10.3 Clock Input To Tcnt And Count Condition (3)
Table 10.3 Clock Input to TCNT and Count Condition (3) Channel CKS2 CKS1 CKS0 TMR_B TMR_A Notes: * If the TMR_B clock input is set as the TCNT_A overflow signal and the TMR_A clock input is set as the TCNT_B compare-match signal simultaneously, a count-up clock cannot be generated.
Page 230: Timer Control/Status Register (Tcsr)
10.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. TCSR_0 Initial Bit Name Value CMFB CMFA ADTE Note: Only 0 can be written, for flag clearing. Rev. 1.00, 05/04, page 196 of 544 Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_0 and TCORB_0 match...
Page 231 TCSR_1 Initial Bit Name Value CMFB CMFA — Note: Only 0 can be written, for flag clearing. Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB R/(W)* Compare-Match Flag A [Setting condition]...
Page 232 TCSR_Y Initial Bit Name Value CMFB CMFA ICIE Notes: 1. Only 0 can be written, for flag clearing. 2. The program development tool (emulator) does not support this pin. Rev. 1.00, 05/04, page 198 of 544 Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing condition]...
Page 233 TCSR_X Initial Bit Name Value CMFB CMFA Note: Only 0 can be written, for flag clearing. Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_X and TCORB_X match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB R/(W)* Compare-Match Flag A [Setting condition]...
Page 234 TCSR_B Initial Bit Name Value CMFB CMFA ICIE Notes: * Only 0 can be written, for flag clearing. Rev. 1.00, 05/04, page 200 of 544 Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_B and TCORB_B match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB R/(W)*...
Page 235 TCSR_A Initial Bit Name Value CMFB CMFA Note: Only 0 can be written, for flag clearing. Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_A and TCORB_A match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB R/(W)* Compare-Match Flag A [Setting condition]...
Page 236: Time Constant Register (Tcorc)
10.3.6 Time Constant Register (TCORC) TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always compared with TCNT. When a match is detected, a compare-match C signal is generated. However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of TICR is disabled.
Page 237: Timer Connection Register I (Tconri)
10.3.9 Timer Connection Register I (TCONRI) TCONRI controls the input capture function. Initial Bit Name Value 7 to 5 — All 0 ICST 3 to 0 — All 0 10.3.10 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers. Initial Bit Name Value...
Page 238: Timer Xy Control Register (Tcrxy)
Table 10.4 Registers Accessible by TMR_X/TMR_Y TMRX/Y H'FFF0 H'FFF1 TMR_X TMR_X TCR_X TCSR_X TMR_Y TMR_Y TCR_Y TCSR_Y 10.3.11 Timer XY Control Register (TCRXY) TCRXY selects the TMR_X and TMR_Y output pins and internal clock. Initial Bit Name Value IOSX IOSY CKSX CKSY 3 to 0...
Page 239: Timer Ab Control Register (Tcrab)
10.3.12 Timer AB Control Register (TCRAB) TCRAB selects the internal clock or controls the input capture function in the TMR_A and TMR_B. Initial Bit Name Value  7, 6 All 0 CKSA CKSB ICST 2 to 0 — Note: The program development tool (emulator) does not support TCRXY. Description Reserved The initial value should not be modified.
Page 240: Operation
10.4 Operation 10.4.1 Pulse Output Figure 10.4 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0 so that TCNT is cleared according to the compare match of TCORA, and then set the CCLR0 bit to 1. 2.
Page 241: Operation Timing
10.5 Operation Timing 10.5.1 TCNT Count Timing Figure 10.5 shows the TCNT count timing with an internal clock source. Figure 10.6 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both edges.
Page 242: Timing Of Timer Output At Compare-Match
φ TCNT TCOR Compare-match signal Figure 10.7 Timing of CMF Setting at Compare-Match 10.5.3 Timing of Timer Output at Compare-Match When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 10.8 shows the timing of timer output when the output is set to toggle by a compare-match A signal.
Page 243: Tcnt External Reset Timing
10.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 10.10 shows the timing of clearing the counter by an external reset input.
Page 244: Tmr_0 And Tmr_1 Cascaded Connection
10.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, the 16-bit count mode or compare-match count mode is available. 10.6.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer...
Page 245: Tmr_Y And Tmr_X Cascaded Connection
10.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected by the settings of the CKSX and CKSY bits in TCRXY. 10.7.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_Y are set to B'100 and the CKSY bit in TCRXY is set to 1, the...
Page 246: Input Capture Operation
10.7.3 Input Capture Operation TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF.
Page 247: Input Capture Operation
10.8.3 Input Capture Operation TMR_A has input capture registers (TICRR_A and TICRF_A). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIA (TMR_A input capture input signal) is detected after its rising edge has been detected, the value of TCNT_A at that time is transferred to both TICRR and TICRF.
Page 248: Table 10.5 Input Capture Signal Selection
Selection of Input Capture Signal Input: TMRIX (input capture input signal of TMR_X) is selected according to the setting of the ICST bit in TCONRI. The input capture signal selection is shown in table 10.5. Table 10.5 Input Capture Signal Selection TCONRI Bit 4 ICST...
Page 249: Interrupt Sources
10.9 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate an ICIX interrupt. TMR_A can generate four types of interrupts, CMIA, CMIB, OVI and ICIA. Table 10.7 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR.
Page 250: Usage Notes
10.10 Usage Notes 10.10.1 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T 10.14, clearing takes priority and the counter write is not performed. φ Address Internal write signal Counter clear signal TCNT Note: * TMR_A, TMR_B Figure 10.14 Conflict between TCNT Write and Clear...
Page 251: 10.10.3 Conflict Between Tcor Write And Compare-Match
10.10.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T TCOR write takes priority and the compare-match signal is disabled. With TMR_X, and TMR_A, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled.
Page 252: 10.10.5 Switching Of Internal Clocks And Tcnt Operation
10.10.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 10.9 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected.
Page 253: 10.10.6 Mode Setting With Cascaded Connection
Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from high to low level∗ Clock switching from high to high level Notes: 1. Includes switching from low to stop, and from stop to low. 2. Includes switching from stop to high. 3.
Page 254 Rev. 1.00, 05/04, page 220 of 544...
Page 255: Section 11 Watchdog Timer (Wdt)
Section 11 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can output an overflow signal (RESO) externally.
Page 256: Figure 11.1 Block Diagram Of Wdt
WOVI0 (Interrupt request signal) Internal NMI (Interrupt request signal* RESO signal* Internal reset signal* WOVI1 (Interrupt request signal) Internal NMI (Interrupt request signal* RESO signal* Internal reset signal* [Legend] TCSR_0 : Timer control/status register_0 TCNT_0 : Timer counter_0 TCSR_1 : Timer control/status register_1 TCNT_1 : Timer counter_1 Notes: 1.
Page 257: Input/Output Pins
11.2 Input/Output Pins The WDT has the pins listed in table 11.1. Table 11.1 Pin Configuration Name Reset output pin External sub-clock input pin EXCL 11.3 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers.
Page 258: Timer Control/Status Register (Tcsr)
11.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. • TCSR_0 Initial Bit Name Value WT/IT — RST/NMI Rev. 1.00, 05/04, page 224 of 544 Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00).
Page 259 Initial Bit Name Value CKS2 CKS1 CKS0 Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice. • TCSR_1 Initial Bit Name Value...
Page 260 Initial Bit Name Value RST/NMI CKS2 CKS1 CKS0 Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice. Rev. 1.00, 05/04, page 226 of 544 Description Prescaler Select Selects the clock source to be input to TCNT.
Page 261: Operation
11.4 Operation 11.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated.
Page 262: Figure 11.2 Watchdog Timer Mode (Rst/Nmi = 1) Operation
TCNT value H'FF H'00 WT/IT = 1 TME = 1 RESO signal Internal reset signal [Legend] Timer mode select bit WT/IT: Timer enable bit TME: Overflow flag OVF: Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0.
Page 263: Interval Timer Mode
11.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 11.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit of TCSR is set to 1.
Page 264: Reso Signal Output Timing
RESO Signal Output Timing 11.4.3 When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin.
Page 265: Usage Notes
11.6 Usage Notes 11.6.1 Notes on Register Access The watchdog timer's registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a word transfer instruction.
Page 266: Conflict Between Timer Counter (Tcnt) Write And Increment
11.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.7 shows this operation. φ...
Page 267: System Reset By Reso Signal
System Reset by RESO Signal 11.6.5 Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI from being initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI. To reset the entire system by the RESO signal, use the circuit as shown in figure 11.8.
Page 268 Rev. 1.00, 05/04, page 234 of 544...
Page 269: Section 12 Serial Communication Interface (Sci)
Section 12 Serial Communication Interface (SCI) This LSI has a serial communication interface (SCI). The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 270: Input/Output Pins
ExRxD*/RxD ExTxD*/TxD ExSCK*/SCK [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register Note: * The program development tool (emulator) does not support this function. 12.2 Input/Output Pins Table 12.1 shows the input/output pins for each SCI channel. Table 12.1 Pin Configuration Channel Symbol*...
Page 271: Register Descriptions
12.3 Register Descriptions The SCI has the following registers. • Receive shift register (RSR) • Receive data register (RDR) • Transmit data register (TDR) • Transmit shift register (TSR) • Serial mode register (SMR) • Serial control register (SCR) • Serial status register (SSR) •...
Page 272: Transmit Shift Register (Tsr)
12.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU.
Page 273: Serial Control Register (Scr)
Initial Bit Name Value CKS1 CKS0 12.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, refer to section 12.7, Interrupt Sources.
Page 274 Initial Bit Name Value MPIE TEIE CKE1 CKE0 [Legend] Don't care Rev. 1.00, 05/04, page 240 of 544 Description Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled.
Page 275: Serial Status Register (Ssr)
12.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Initial Bit Name Value TDRE RDRF ORER Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data.
Page 276 Initial Bit Name Value TEND MPBT Note: Only 0 can be written, to clear the flag. Rev. 1.00, 05/04, page 242 of 544 Description R/(W)* Parity Error [Setting condition] • When a parity error is detected during reception [Clearing condition] •...
Page 277: Serial Interface Mode Register (Scmr)
12.3.8 Serial Interface Mode Register (SCMR) SCMR selects SCI functions and its format. Initial Bit Name Value 7 to 4 — All 1 SDIR SINV — SMIF Description Reserved These bits are always read as 1 and cannot be modified. Data Transfer Direction Selects the serial/parallel conversion format.
Page 278: Bit Rate Register (Brr)
12.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 12.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode.
Page 279: Table 12.3 Brr Settings For Various Bit Rates (Asynchronous Mode) (1)
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Bit Rate Error (bit/s) 0.03 0.16 0.16 0.16 1200 0.16 2400 0.16 4800 0.16 9600 0.16 19200 — — — 31250 0.00 38400 — — — [Legend] —: Can be set, but there will be a degree of error. Note: Make the settings so that the error does not exceed 1%.
Page 280: Table 12.3 Brr Settings For Various Bit Rates (Asynchronous Mode) (2)
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Bit Rate Error (bit/s) –0.44 0.16 0.16 0.16 1200 0.16 2400 0.16 4800 0.16 9600 –2.34 19200 –2.34 31250 0.00 38400 –2.34 Operating Frequency φ (MHz) 9.8304 Bit Rate Error (bit/s) –0.26...
Page 281: Table 12.4 Maximum Bit Rate For Each Frequency (Asynchronous Mode)
Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Bit Rate φ (MHz) (bit/s) 125000 4.9152 153600 156250 187500 6.144 192000 7.3728 230400 250000 Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) External Input φ (MHz) Clock (MHz) 1.0000 4.9152...
Page 282: Table 12.6 Brr Settings For Various Bit Rates (Clocked Synchronous Mode)
Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate (bit/s) — 2.5k 100k 250k 500k 2.5M [Legend] Blank: Cannot be set. —: Can be set, but there will be a degree of error. Continuous transfer or reception is not possible. Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) φ...
Page 283: Serial Pin Select Register (Spsr)
12.3.10 Serial Pin Select Register (SPSR) SPSR selects the serial I/O pins. SPSR should be set before initialization. Do not set during communication. Initial Name Value SPS1 6 to 0 — All 0 Note: The program development tool (emulator) does not support SPSR. 12.4 Operation in Asynchronous Mode Figure 12.2 shows the general format for asynchronous serial communication.
Page 284: Data Transfer Format
12.4.1 Data Transfer Format Table 12.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 12.5, Multiprocessor Communication Function. Table 12.8 Serial Transfer Formats (Asynchronous Mode) SMR Settings —...
Page 285: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 286: Figure 12.4 Relation Between Output Clock And Transmit Data Phase (Asynchronous Mode)
12.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
Page 287: Sci Initialization (Asynchronous Mode)
12.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 12.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 288: Data Transmission (Asynchronous Mode)
12.4.5 Data Transmission (Asynchronous Mode) Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 289: Figure 12.7 Sample Serial Transmission Flowchart
Initialization Start transmission Read TDRE flag in SSR TDRE = 1 Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Read TEND flag in SSR TEND = 1 Break output? Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 <End>...
Page 290: Serial Data Reception (Asynchronous Mode)
12.4.6 Serial Data Reception (Asynchronous Mode) Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 291: Figure 12.9 Sample Serial Reception Flowchart (1)
Table 12.9 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* ORER Note: The RDRF flag retains the state it had before data reception. Initialization Start reception Read ORER, PER, and FER flags in SSR PER ∨ FER ∨ ORER = 1 Read RDRF flag in SSR RDRF = 1 Read receive data in RDR, and...
Page 292: Figure 12.9 Sample Serial Reception Flowchart (2)
Overrun error processing Framing error processing Figure 12.9 Sample Serial Reception Flowchart (2) Rev. 1.00, 05/04, page 258 of 544 Error processing ORER = 1 FER = 1 Break? PER = 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End>...
Page 293: Multiprocessor Communication Function
12.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 294: Multiprocessor Serial Data Transmission
12.5.1 Multiprocessor Serial Data Transmission Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
Page 295: Multiprocessor Serial Data Reception
12.5.2 Multiprocessor Serial Data Reception Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 296: Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)
Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ∨ ORER = 1 Read RDRF flag in SSR RDRF = 1 Read receive data in RDR This station’s ID? Read ORER and FER flags in SSR FER ∨...
Page 297: Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)
Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2) Clear RE bit in SCR to 0 Rev.
Page 298: Operation In Clocked Synchronous Mode
12.6 Operation in Clocked Synchronous Mode Figure 12.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
Page 299: Sci Initialization (Clocked Synchronous Mode)
12.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 300: Serial Data Transmission (Clocked Synchronous Mode)
12.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 12.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 301: Figure 12.17 Sample Serial Transmission Flowchart
Initialization Start transmission Read TDRE flag in SSR TDRE = 1 Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Read TEND flag in SSR TEND = 1 Clear TE bit in SCR to 0 <End>...
Page 302: Serial Data Reception (Clocked Synchronous Mode)
12.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR.
Page 303: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
Initialization Start reception Read ORER flag in SSR ORER = 1 Read RDRF flag in SSR RDRF = 1 Read receive data in RDR and clear RDRF flag in SSR to 0 All data received? Clear RE bit in SCR to 0 <End>...
Page 304: Figure 12.20 Sample Flowchart Of Simultaneous Serial Transmission And Reception
Initialization Start transmission/reception Read TDRE flag in SSR TDRE = 1 Write transmit data to TDR and clear TDRE flag in SSR to 0 Read ORER flag in SSR ORER = 1 Read RDRF flag in SSR RDRF = 1 Read receive data in RDR, and clear RDRF flag in SSR to 0 All data received?
Page 305: Interrupt Sources
12.7 Interrupt Sources Table 12.10 shows the interrupt sources in serial communication interface. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated.
Page 306: Usage Notes
12.8 Usage Notes 12.8.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 20, Power-Down Modes.
Page 307: Sci Operations During Mode Transitions
12.8.6 SCI Operations during Mode Transitions Transmission: Before making a transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation.
Page 308: Figure 12.21 Sample Flowchart For Mode Transition During Transmission
Transmission All data transmitted? Read TEND flag in SSR TEND = 1 TE = 0 Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? Initialization Start transmission Figure 12.21 Sample Flowchart for Mode Transition during Transmission TE bit output pin Port...
Page 309: Internal Clock
TE bit output pin Port Marking output input/output output pin Port Note: * Initialized in software standby mode Figure 12.23 Pin States during Transmission in Clocked Synchronous Mode Reception Read RDRF flag in SSR RDRF = 1 Read receive data in RDR RE = 0 Make transition to software standby mode etc.
Page 310: Switching From Sck Pins To Port Pins
12.8.7 Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 12.25. SCK/Port Bit 6 Data...
Page 311: Section 13 I C Bus Interface (Iic)
Section 13 I This LSI has a two-channel I subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however. 13.1 Features • Selection of addressing format or non-addressing format ...
Page 312: Figure 13.1 Block Diagram Of I
• Selectable input/output pins*  Pins, PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB, are selectable for the I C bus input/output pin in each channel. Note: * The program development tool (emulator) does not support this function. Figure 13.1 shows a block diagram of the I pin connections to external circuits.
Page 313: Figure 13.2 I C Bus Interface Connections (Example: This Lsi As Master)
(Master) This LSI Figure 13.2 I C Bus Interface Connections (Example: This LSI as Master) (Slave 1) (Slave 2) Rev. 1.00, 05/04, page 279 of 544...
Page 314: Input/Output Pins
13.2 Input/Output Pins Table 13.1 summarizes the input/output pins used by the I for each channel can be selected from the three pins*. The serial data I/O pin for each channel can be selected form the three pins*. Do not set multiple pins as the serial clock I/O pin or serial data I/O pin for a single channel.
Page 315: Register Descriptions
13.3 Register Descriptions The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed.
Page 316: C Bus Data Register (Icdr)
13.3.1 C Bus Data Register (ICDR) ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is internally divided into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among these three registers are performed automatically in accordance with changes in the bus state, and they affect the status of internal flags such as ICDRE and ICDRF.
Page 317: Slave Address Register (Sar)
13.3.2 Slave Address Register (SAR) SAR sets the slave address and selects the communication format. If the LSI is in slave mode with the I C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device.
Page 318: Second Slave Address Register (Sarx)
13.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. If the LSI is in slave mode with the I C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device.
Page 319: Table 13.2 Communication Format
Table 13.2 Communication Format SARX Operating Mode • • • • • • • • Clocked synchronous serial format • • • I C bus format: addressing format with an acknowledge bit • Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master mode only C bus format SAR and SARX slave addresses recognized...
Page 320: C Bus Mode Register (Icmr)
13.3.4 C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Initial Bit Name Value WAIT CKS2 CKS1 CKS0 Rev. 1.00, 05/04, page 286 of 544 Description MSB-First/LSB-First Select 0: MSB-first...
Page 321 Initial Bit Name Value Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low.
Page 322: Table 13.3 I 2 C Transfer Rate
Table 13.3 I C Transfer Rate STCR Bits 5 and 6 Bit 5 Bit 4 IICX CKS2 CKS1 Rev. 1.00, 05/04, page 288 of 544 ICMR Bit 3 CKS0 Clock φ/28 φ/40 φ/48 φ/64 φ/80 φ/100 φ/112 φ/128 φ/56 φ/80 φ/96 φ/128 φ/160...
Page 323: C Bus Control Register (Iccr)
13.3.5 C Bus Control Register (ICCR) ICCR controls the I C bus interface and performs interrupt flag confirmation. Initial Bit Name Value IEIC Description C Bus Interface Enable 0: I C bus interface modules are stopped and I interface module internal state is initialized. SAR and SARX can be accessed.
Page 324 Initial Bit Name Value ACKE Rev. 1.00, 05/04, page 290 of 544 Description [MST clearing conditions] 1. When 0 is written by software 2. When lost in bus contention in I master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2.
Page 325 Initial Bit Name Value BBSY Note: The value in BBSY flag does not change even if written. Description R/W* Bus Busy Start Condition/Stop Condition Prohibit In master mode: • Writing 0 in BBSY and 0 in SCP: A stop condition is issued •...
Page 326 Initial Name Value IRIC Rev. 1.00, 05/04, page 292 of 544 Description R/(W)* C Bus Interface Interrupt Request Flag Indicates that the I interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
Page 327 Initial Bit Name Value IRIC Note: Only 0 can be written, to clear the flag. When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer.
Page 328: Table 13.4 Flags And Transfer States (Master Mode)
Table 13.4 Flags and Transfer States (Master Mode) ESTP BBSY STOP 1↑ — 0↓ 0↓ — 0↓ [Legend] 0-state retained 1-state retained —: Previous state retained ↓ Cleared to 0 ↑ Set to 1 Rev. 1.00, 05/04, page 294 of 544 IRTR AASX 0↓...
Page 329: Table 13.5 Flags And Transfer States (Slave Mode)
Table 13.5 Flags and Transfer States (Slave Mode) ESTP BBSY STOP 1↑ 1↑/0 1↑/0 IRTR AASX 0↓ — 1↑ — 1↑ 1↑ 1↑ 1↑ — — — — — 1↑/0 — — — — — 0↓ 0↓ — — — —...
Page 330: Table 13.5 Flags And Transfer States (Slave Mode) (Cont)
Table 13.5 Flags and Transfer States (Slave Mode) (cont) ESTP BBSY STOP — 0↓ 1↑/0 0/1↑ [Legend] 0-state retained 1-state retained —: Previous state retained ↓ Cleared to 0 ↑ Set to 1 Notes: 1. Set to 1 when 1 is received as a R/W bit following an address. 2.
Page 331: C Bus Status Register (Icsr)
13.3.6 C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 13.4 and 13.5. Initial Bit Name Value ESTP STOP IRTR Description R/(W)* Error Stop Condition Detection Flag This bit is valid in I [Setting condition] When a stop condition is detected during frame transfer.
Page 332 Initial Bit Name Value AASX Rev. 1.00, 05/04, page 298 of 544 Description R/(W)* Second Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX.
Page 333 Initial Bit Name Value Description R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Page 334 Initial Bit Name Value ACKB Note: Only 0 can be written to clear the flag. Rev. 1.00, 05/04, page 300 of 544 Description Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] When 1 is received as the acknowledge bit when ACKE = 1 in transmit mode [Clearing conditions] •...
Page 335: Ddc Switch Register (Ddcswr)
13.3.7 DDC Switch Register (DDCSWR) DDCSWR controls IIC internal latch clearance. Initial Bit Name Value 7 to 5 — All 0 — CLR3 CLR2 CLR1 CLR0 Note: This bit is always read as 1. Description Reserved The initial value should not be changed. Reserved IIC Clear 3 to 0 Controls initialization of the internal state of IIC_0 and...
Page 336: C Bus Extended Control Register (Icxr)
13.3.8 C Bus Extended Control Register (ICXR) ICXR enables or disables the I operation, and indicates the status of receive/transmit operations. Initial Bit Name Value STOPIM HNDS Rev. 1.00, 05/04, page 302 of 544 C bus interface interrupt generation and continuous receive Description Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the...
Page 337 Initial Bit Name Value ICDRF Description Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out.
Page 338 Initial Bit Name Value ICDRE Rev. 1.00, 05/04, page 304 of 544 Description Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has...
Page 339 Initial Bit Name Value ALIE ALSL FNC1 FNC0 Description Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. Arbitration Lost Condition Select Selects the condition under which arbitration is lost.
Page 340: Port G Control Register
13.3.9 Port G Control Register (PGCTL) PGCTL selects the input/output pin for IIC. Initial Bit Name Value IIC1BS IIC1AS  4, 5 All 0 IIC0BS IIC0AS  1, 0 All 0 Notes: 1. The program development tool (emulator) does not support this function. 2.
Page 341: Operation
13.4 Operation The I C bus interface has an I 13.4.1 C Bus Data Format The I C bus format is an addressing format with an acknowledge bit. This is shown in figure 13.3. The first frame following a start condition always consists of 9 bits. The serial format is a non-addressing format with no acknowledge bit.
Page 342: Figure 13.5 I C Bus Timing
1 to 7 Table 13.6 I C Bus Data Format Symbols Legend Start condition. The master device drives SDA from high to low while SCL is high. Slave address. The master device selects the slave device. Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge.
Page 343: Initialization
13.4.2 Initialization Initialize the IIC by the procedure shown in figure 13.6 before starting transmission/reception of data. Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) (MSTPCRL) Set IICE = 1 in STCR Set ICE = 0 in ICCR Set SAR and SARX Set ICE = 1 in ICCR Set ICSR...
Page 344: Figure 13.7 Sample Flowchart For Operations In Master Transmit Mode
Initialize IIC Read BBSY flag in ICCR BBSY = 0? Set MST = 1 and TRS = 1 in ICCR Set BBSY =1 and SCP = 0 in ICCR Read IRIC flag in ICCR IRIC = 1? Write transmit data in ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR IRIC = 1?
Page 345 The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR (ICDRT) write operations, are described below. 1. Initialize the IIC as described in section 13.4.2, Initialization. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3.
Page 346: Figure 13.8 Example Of Operation Timing In Master Transmit Mode (Mls = Wait = 0)
12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Start condition generation (master output) (master output)
Page 347: Figure 13.9 Example Of Stop Condition Issuance Operation Timing In Master Transmit Mode (Mls = Wait = 0)
(master output) Bit 0 (master output) Data 1 (slave output) ICDRE IRIC IRTR ICDR Data 1 User processing [9] ICDR write Figure 13.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0) Bit 7 Bit 6 Bit 5 Bit 4...
Page 348: Master Receive Operation
13.4.4 Master Receive Operation In I C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation.
Page 349 The reception procedure and operations using the HNDS function, by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception, are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting).
Page 350: Figure 13.11 Example Of Operation Timing In Master Receive Mode (Mls = Wait = 0, Hnds = 1)
Master transmit mode Master receive mode SCL is fixed low until ICDR is read (master output) (slave output) (master output) IRIC IRTR ICDRF ICDRR User processing [1] TRS=0 clear Figure 13.11 Example of Operation Timing in Master Receive Mode SCL is fixed low until ICDR is read (master output) Bit 1 Bit 0...
Page 351: Figure 13.13 Sample Flowchart For Operations In Master Receive Mode (Receiving Multiple Bytes) (Wait = 1)
Receive Operation Using the Wait Function: Figures 13.13 and 13.14 show the sample flowcharts for the operations in master receive mode (WAIT = 1). Clear IRIC flag in ICCR Wait for one clock pulse Clear IRIC flag in ICCR Set BBSY= 0 and SCP= 0 Figure 13.13 Sample Flowchart for Operations in Master Receive Mode Master receive mode Set TRS = 0 in ICCR...
Page 352: Figure 13.14 Sample Flowchart For Operations In Master Receive Mode (Receiving A Single Byte) (Wait = 1)
Slave receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 0 in ICMR Read ICDR Read IRIC flag in ICCR IRIC = 1? Set ACKB = 1 in ICSR Set TRS = 1 in ICCR Clear IRIC flag in ICCR...
Page 353 The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially received in synchronization with ICDR (ICDRR) read operations, are described below. The following describes the multiple-byte reception procedure. In single-byte reception, some steps of the following procedure are omitted. At this time, follow the procedure shown in figure 13.14.
Page 354: Figure 13.15 Example Of Master Receive Mode Operation Timing (Mls = Ackb = 0, Wait = 1)
12. The IRIC flag is set to 1 in either of the following cases.  At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared.
Page 355: Slave Receive Operation
[8] Wait for one clock pulse (master output) Bit 0 (slave output) Data 2 (master output) IRIC IRTR [4] IRTR=0 [4] IRTR=1 ICDR Data 1 User processing [6] IRIC clear [7] Set ACKB=1 Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode 13.4.5 Slave Receive Operation In I...
Page 356: Figure 13.17 Sample Flowchart For Operations In Slave Receive Mode (Hnds = 1)
Slave receive mode Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR and HNDS = 1 in ICXR Read IRIC flag in ICCR ICDRF = 1? Read ICDR, clear IRIC flag Read IRIC flag in ICCR IRIC = 1? Clear IRIC flag in ICCR...
Page 357 The reception procedure and operations using the HNDS bit function, by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. 1. Initialize the IIC as described in section 13.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0.
Page 358: Figure 13.18 Example Of Slave Receive Mode Operation Timing (1) (Mls = 0, Hnds= 1)
Start condition generation (Pin waveform) (master output) (slave output) (master output) (slave output) IRIC ICDRF ICDRS ICDRR User processing [2] ICDR read Figure 13.18 Example of Slave Receive Mode Operation Timing (1) [7] SCL is fixed low until ICDR is read (master output) (slave output) Bit 0...
Page 359: Figure 13.20 Sample Flowchart For Operations In Slave Receive Mode (Hnds = 0)
Continuous Receive Operation: Figure 13.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0). Slave receive mode Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR ICDRF = 1? Read ICDR...
Page 360 The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in section 13.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0.
Page 361: Figure 13.21 Example Of Slave Receive Mode Operation Timing (1) (Mls = Ackb = 0, Hnds = 0)
Start condition issuance (master output) Bit 7 Bit 6 (master output) (slave output) IRIC ICDRF ICDRS ICDRR User processing Figure 13.21 Example of Slave Receive Mode Operation Timing (1) (master output) Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 (master output) Data n-2 [11]...
Page 362: Slave Transmit Operation
13.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 13.23 shows the sample flowchart for the operations in slave transmit mode.
Page 363 In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2.
Page 364: Figure 13.24 Example Of Slave Transmit Mode Operation Timing (Mls = 0)
10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1.
Page 365: Iric Setting Timing And Scl Control
13.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock.
Page 366: Figure 13.26 Iric Setting Timing And Scl Control (2)
When WAIT = 1, and FS = 0 or FSX = 0 (I IRIC User processing (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. IRIC User processing (b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception. Figure 13.26 IRIC Setting Timing and SCL Control (2) Rev.
Page 367: Figure 13.27 Iric Setting Timing And Scl Control (3)
When FS = 1 and FSX = 1 (clocked synchronous serial format) IRIC User processing (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception. IRIC User processing (b) Data transfer ends with ICDRE =1 at transmission, or ICDRF = 1 at reception. Figure 13.27 IRIC Setting Timing and SCL Control (3) Clear IRIC Clear IRIC...
Page 368: Noise Canceller
13.4.8 Noise Canceller The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched internally. Figure 13.28 shows a block diagram of the noise canceller. The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Page 369: Initialization Of Internal State
13.4.9 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 13.3.7, DDC Switch Register (DDCSWR).
Page 370: Interrupt Sources
The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect.
Page 371: Usage Notes
13.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruction to generate a stop condition is issued before the start condition is output to the I condition will be output correctly. To output the start condition followed by the stop condition, after issuing the instruction that generates the start condition, read DR in each I pin, and check that SCL and SDA are both low.
Page 372: Table 13.9 Permissible Scl Rise Time
5. The I C bus interface specification for the SCL rise time t speed mode). In master mode, the I one bit at a time during communication. If t the time determined by the input clock of the I extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line.
Page 373 Table 13.10 I C Bus Timing (with Maximum Influence of t Item Indication 0.5 t (–t Standard mode SCLHO SCLO High-speed mode 0.5 t (–t Standard mode SCLLO SCLO High-speed mode 0.5 t –1 t Standard mode BUFO SCLO (–t High-speed mode 0.5 t –1 t...
Page 374: Figure 13.29 Notes On Reading Master Receive Data
7. Notes on ICDR read at end of master reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
Page 375: Figure 13.30 Flowchart For Start Condition Issuance Instruction For Retransmission
8. Notes on start condition issuance for retransmission Figure 13.30 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. Write the transmit data to ICDR after the start condition for retransmission is issued and then the start condition is actually generated.
Page 376: Figure 13.31 Stop Condition Issuance Timing
9. Note on when I C bus interface stop condition instruction is issued In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low.
Page 377: Figure 13.32 Iric Flag Clearing Timing When Wait = 1
10. Note on IRIC flag clear when the wait function is used If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be inserted by driving the SCL pin low is used when the wait function is used in I master mode, the IRIC flag should be cleared after determining that the SCL is low, as described below.
Page 378: Figure 13.33 Icdr Read And Iccr Access Timing In Slave Transmit Mode
11. Note on ICDR read and ICCR access in slave transmit mode In I C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 13.33. However, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling.
Page 379: Figure 13.34 Trs Bit Set Timing In Slave Mode
12. Note on TRS bit setting in slave mode In I C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 13.34), the bit value becomes valid immediately when it is set.
Page 380 13. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly.
Page 381: Module Stop Mode Setting
C bus interface (Master transmit mode) Other device (Master transmit mode) C bus interface (Slave receive mode) • Receive address is ignored Figure 13.35 Diagram of Erroneous Operation when Arbitration is Lost Though it is prohibited in the normal I bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode.
Page 382 Rev. 1.00, 05/04, page 348 of 544...
Page 383: Section 14 Keyboard Buffer Controller
Section 14 Keyboard Buffer Controller This LSI has three on-chip keyboard buffer controller channels. The keyboard buffer controller is provided with functions conforming to the PS/2 interface specifications. Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc.
Page 384: Input/Output Pins
Figure 14.2 shows how the keyboard buffer controller is connected. System side KCLK in KCLK out KD in KD out Keyboard buffer controller (This LSI) Figure 14.2 Keyboard Buffer Controller Connection 14.2 Input/Output Pins Table 14.1 lists the input/output pins used by the keyboard buffer controller. Table 14.1 Pin Configuration Channel Name...
Page 385: Register Descriptions
14.3 Register Descriptions The keyboard buffer controller has the following registers for each channel. • Keyboard control register H (KBCRH) • Keyboard control register L (KBCRL) • Keyboard data buffer register (KBBR) 14.3.1 Keyboard Control Register H (KBCRH) KBCRH indicates the operating status of the keyboard buffer controller. Initial Bit Name Value...
Page 386 Initial Bit Name Value KBIE Note: Only 0 can be written for clearing the flag. Rev. 1.00, 05/04, page 352 of 544 Description Keyboard Interrupt Enable Enables or disables interrupts from the keyboard buffer controller to the CPU. 0: Interrupt requests are disabled 1: Interrupt requests are enabled R/(W)* Keyboard Buffer Register Full...
Page 387: Keyboard Control Register L (Kbcrl)
14.3.2 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffer controller pin output. Initial Bit Name Value KCLKO — RXCR3 RXCR2 RXCR1 RXCR0 Description Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled Keyboard Clock Out...
Page 388: Keyboard Data Buffer Register (Kbbr)
14.3.3 Keyboard Data Buffer Register (KBBR) KBBR stores receive data. Its value is valid only when KBF = 1. Initial Bit Name Value Rev. 1.00, 05/04, page 354 of 544 Description Keyboard Data 7 to 0 8-bit read only data. Initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode, and when KBIOE is cleared to 0.
Page 389: Operation
14.4 Operation 14.4.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order.
Page 390: Transmit Operation
KCLK (pin state) Start (pin state) KCLK (input) KCLK (output) KB7 to KB0 Previous data [1] [2] [3] 14.4.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order.
Page 391: Figure 14.5 Sample Transmit Processing Flowchart (1)
Start Set KBIOE bit Read KBCRH KCLKI and KDI bits both Set I/O inhibit (KCLKO = 0) KDO remains at 1 KBE = 0 (KBBR reception prohibited) Wait Set start bit (KDO = 0) KCLKO remains at 0 Set I/O inhibit (KCLKO = 1) KDO remains at 0 i = 0 Read KBCRH...
Page 392: Figure 14.5 Sample Transmit Processing Flowchart (2)
Read KBCRH KCLKI = 0? KDI = 0? Read KBCRH KCLK = 1? Transmit end state (KCLK = high, KD = high) To receive operation or transmit operation Note: * To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low. Figure 14.5 Sample Transmit Processing Flowchart (2) KCLK (pin state)
Page 393: Receive Abort
14.4.3 Receive Abort This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc. In this case, the system holds the clock low. During reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when the keyboard output clock is high.
Page 394: Figure 14.7 Sample Receive Abort Processing Flowchart (2)
Processing 1 Receive operation ends normally Receive data processing Clear KBF flag (KCLK = High) Transmit enabled state. If there is transmit data, the data is transmitted. Figure 14.7 Sample Receive Abort Processing Flowchart (2) Reception in progress KCLK (pin state) (pin state) KCLK (input)
Page 395: Kclki And Kdi Read Timing
14.4.4 KCLKI and KDI Read Timing Figure 14.9 shows the KCLKI and KDI read timing. Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 14.9 KCLKI and KDI Read Timing 14.4.5 KCLKO and KDO Write Timing...
Page 396: Kbf Setting Timing And Kclk Control
14.4.6 KBF Setting Timing and KCLK Control Figure 14.11 shows the KBF setting timing and the KCLK pin states. KCLK (pin) Internal KCLK Falling edge signal RXCR3 to B'1010 RXCR0 KCLK (output) Note: * clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode.
Page 397: Receive Timing
14.4.7 Receive Timing Figure 14.12 shows the receive timing. KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 Internal KD (KDI) KBBR7 to KBBR0 Note: * clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode.
Page 398: Kclk Fall Interrupt Operation
14.4.8 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRL to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 14.13 shows the setting method and an example of operation. Start Set KBIOE KBE = 0...
Page 399: Usage Notes
14.5 Usage Notes 14.5.1 KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected.
Page 400: Module Stop Mode Setting
14.5.2 Module Stop Mode Setting Keyboard buffer controller operation can be enabled or disabled using the module stop control register. The initial setting is for keyboard buffer controller operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 20, Power-Down Modes. Rev.
Page 401: Section 15 Host Interface (Lpc)
Section 15 Host Interface (LPC) This LSI has an on-chip LPC interface. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. This LPC module supports only I/O read cycle and I/O write cycle transfers.
Page 402: Figure 15.1 Block Diagram Of Lpc
Figure 15.1 shows a block diagram of the LPC. TWR0MW TWR1–15 Cycle detection Serial → parallel conversion LAD0 to LAD3 H'0060/64 H'0062/66 Serial ← parallel conversion SYNC output TWR0SW TWR1–15 [Legend] HICR0 to HICR3: Host interface control registers 0 to 3 LADR3H, 3L: LPC channel 3 address register 3H and 3L IDR1 to IDR3:...
Page 403: Section 15 Host Interface (Lpc)
15.2 Input/Output Pins Table 15.1 lists the input and output pins of the LPC module. Table 15.1 Pin Configuration Name LPC address/ data 3 to 0 LPC frame LPC reset LPC clock Serialized interrupt request SERIRQ LSCI general output LSMI general output PME general output GATE A20 LPC clock run...
Page 404 15.3 Register Descriptions The LPC has the following registers. • Host interface control register 0 (HICR0) • Host interface control register 1 (HICR1) • Host interface control register 2 (HICR2) • Host interface control register 3 (HICR3) • LPC channel 3 address registers (LADR3H, LADR3L) •...
Page 405: Input/Output Pins
15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) HICR0 and HICR1 contain control bits that enable or disable host interface functions, control bits that determine pin output and the internal state of the host interface, and status flags that monitor the internal state of the host interface.
Page 406: Register Descriptions
Initial Value Slave Host Description Bit Name FGA20E SDWNE Rev. 1.00, 05/04, page 372 of 544 — Fast A20 Gate Function Enable Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, the normal A20 gate can be implemented by firmware operation of the P81 output.
Page 407: Host Interface Control Registers 0 And 1 (Hicr0, Hicr1)
Initial Value Slave Host Description Bit Name PMEE LSMIE LSCIE [Legend] Don't care — PME output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor is needed to pull the output up to V When the PME output function is used, the DDR bit for P80 must not be set to 1.
Page 408 • HICR1 Initial Bit Name Value Slave LPCBSY CLKREQ Rev. 1.00, 05/04, page 374 of 544 Host Description — LPC Busy Indicates that the host interface is processing a transfer cycle. 0: Host interface is in transfer cycle wait state •...
Page 409 Initial Value Slave Host Description Bit Name IRQBSY LRSTB — — SERIRQ Busy Indicates that the host interface's SERIRQ signal is engaged in transfer processing. 0: SERIRQ transfer frame wait state [Clearing conditions] • LPC hardware reset or LPC software reset •...
Page 410 Initial Value Slave Host Description Bit Name SDWNB PMEB LSMIB LSCIB Rev. 1.00, 05/04, page 376 of 544 — LPC Software Shutdown Bit Controls host interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 15.4.4, Host Interface Shutdown Function (LPCPD).
Page 411 15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3) Bits 6 to 0 in HICR2 control interrupts from the host interface (LPC) module to the slave processor (this LSI). Bit 7 in HICR2 and HICR3 monitor host interface pin states. The pin states can be monitored regardless of the host interface operating state or the operating state of the functions that use pin multiplexing.
Page 412 Initial Bit Name Value Slave Host IBFIE3 R/W — IBFIE2 R/W — IBFIE1 R/W — ERRIE R/W — Note: Only 0 can be written to bits 6 to 4, to clear the flag. • HICR3 Bit Name Initial Value Slave Host Description LFRAME Undefined CLKRUN Undefined SERIRQ...
Page 413: Host Interface Control Registers 2 And 3 (Hicr2, Hicr3)
15.3.3 LPC Channel 3 Address Register (LADR3) LADR3 comprises two 8-bit readable/writable registers that perform LPC channel-3 host address setting and control the operation of the bidirectional data registers. The contents of the address field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1). •...
Page 414: Table 15.2 Register Selection
Table 15.2 Register Selection I/O Address Bit 4 Bit 3 Bit 2 Bit 4 Bit 3 Bit 4 Bit 3 Bit 4 Bit 3 Bit 4 Bit 3 Bit 4 Bit 4 Bit 4 Bit 4 15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) The IDR registers are 8-bit read-only registers for the slave processor (this LSI), and 8-bit write- only registers for the host processor.
Page 415: Lpc Channel 3 Address Register (Ladr3)
15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3) The ODR registers are 8-bit readable/writable registers for the slave processor (this LSI), and 8-bit read-only registers for the host processor. The registers selected from the host according to the I/O address are shown in the following table.
Page 416: Input Data Registers 1 To 3 (Idr1 To Idr3)
I/O Address Bits 15 to 4 Bit 3 0000 0000 0110 0000 0000 0110 • STR1 Initial Bit Name Value Slave Host Description DBU17 DBU16 DBU15 DBU14 C/D1 DBU12 IBF1 OBF1 R/(W)* R Note: Only 0 can be written to clear the flag. Rev.
Page 417: Output Data Registers 1 To 3 (Odr1 To Odr3)
• STR2 Bit Name Initial Value Slave Host Description DBU27 DBU26 DBU25 DBU24 C/D2 DBU22 IBF2 OBF2 Note: Only 0 can be written to clear the flag. Defined by User The user can use these bits as necessary. Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command.
Page 418 • STR3 (TWRE = 1 or SELSTR3 = 0) Initial Bit Name Value Slave Host Description IBF3B OBF3B R/(W)* R MWMF SWMF R/(W)* R Rev. 1.00, 05/04, page 384 of 544 Bidirectional Data Register Input Buffer Full Set to 1 when the host processor writes to TWR15. This is an internal interrupt source to the slave processor (this LSI).
Page 419 Initial Value Slave Host Description Bit Name C/D3 DBU32 IBF3A OBF3A R/(W)* R Note: Only 0 can be written to clear the flag. Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command.
Page 420 • STR3 (TWRE = 0 and SELSTR3 = 1) Initial Bit Name Value Slave DBU37 DBU36 DBU35 DBU34 C/D3 DBU32 IBF3A OBF3A R/(W)* R Note: Only 0 can be written to clear the flag. Rev. 1.00, 05/04, page 386 of 544 Host Description Defined by User The user can use these bits as necessary.
Page 421 15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. • SIRQCR0 Initial Bit Name Value Slave Host SELREQ 0 IEDIR Description —...
Page 422 Initial Value Slave Host Description Bit Name SMIE3B SMIE3A Rev. 1.00, 05/04, page 388 of 544 — Host SMI Interrupt Enable 3B Enables or disables a host SMI interrupt request when OBF3B is set by a TWR15 write. 0: Host SMI interrupt request by OBF3B and SMIE3B is disabled [Clearing conditions] •...
Page 423: Serirq Control Registers 0 And 1 (Sirqcr0, Sirqcr1)
Initial Bit Name Value Slave SMIE2 IRQ12E1 Description — Host SMI Interrupt Enable 2 Enables or disables a host SMI interrupt request when OBF2 is set by an ODR2 write. 0: Host SMI interrupt request by OBF2 and SMIE2 is disabled [Clearing conditions] •...
Page 424 Initial Value Slave Host Bit Name IRQ1E1 R/W — • SIRQCR1 Initial Bit Name Value Slave Host IRQ11E3 R/W — Rev. 1.00, 05/04, page 390 of 544 Description Host IRQ1 Interrupt Enable 1 Enables or disables a host IRQ1 interrupt request when OBF1 is set by an ODR1 write.
Page 425 Initial Value Slave Host Bit Name IRQ10E3 0 IRQ9E3 Description — Host IRQ10 Interrupt Enable 3 Enables or disables a host IRQ10 interrupt request when OBF3A is set by an ODR3 write. 0: Host IRQ10 interrupt request by OBF3A and IRQ10E3 is disabled [Clearing conditions] •...
Page 426 Initial Value Slave Host Bit Name IRQ6E3 R/W — IRQ11E2 R/W — Rev. 1.00, 05/04, page 392 of 544 Description Host IRQ6 Interrupt Enable 3 Enables or disables a host IRQ6 interrupt request when OBF3A is set by an ODR3 write. 0: Host IRQ6 interrupt request by OBF3A and IRQ6E3 is disabled [Clearing conditions]...
Page 427 Initial Value Slave Host Description Bit Name IRQ10E2 IRQ9E2 — Host IRQ10 Interrupt Enable 2 Enables or disables a host IRQ10 interrupt request when OBF2 is set by an ODR2 write. 0: Host IRQ10 interrupt request by OBF2 and IRQ10E2 is disabled [Clearing conditions] •...
Page 428 Initial Value Slave Bit Name IRQ6E2 Rev. 1.00, 05/04, page 394 of 544 Host Description — Host IRQ6 Interrupt Enable 2 Enables or disables a host IRQ6 interrupt request when OBF2 is set by an ODR2 write. 0: Host IRQ6 interrupt request by OBF2 and IRQ6E2 is disabled [Clearing conditions] •...
Page 429 15.3.9 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and specifies the output of the host interrupt request signal of each frame. Bit Name Initial Value Slave Host Description SELSTR3 0 SELIRQ11 SELIRQ10 SELIRQ9 SELIRQ6...
Page 430 15.4 Operation 15.4.1 Host Interface Activation The host interface is activated by setting one of bits LPC3E to LPC1E in HICR0 to 1 in single- chip mode. When the host interface is activated, the related I/O ports (ports 37 to 30, ports 83 and 82) function as dedicated host interface input/output pins.
Page 431: Host Interface Select Register (Hisel)
15.4.2 LPC I/O Cycles There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and bus master I/O write. Of these, the chip's LPC supports only I/O read and I/O write cycles. An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state.
Page 432: Operation
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 15.2 and 15.3. LCLK LFRAME Start LAD3–LAD0 Cycle type, direction, and size Number of clocks Figure 15.2 Typical LFRAME Timing LCLK LFRAME Start LAD3–LAD0 Cycle type, direction, and size 15.4.3 A20 Gate...
Page 433: Lpc I/O Cycles
Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor (this LSI) receives data, it normally uses an interrupt routine activated by the IBF1 interrupt to read IDR1. At this time, firmware copies bit 1 of data following an H'D1 command and outputs it at the gate A20 pin.
Page 434: A20 Gate
Table 15.4 Fast A20 Gate Output Signals Data/Command H'D1 command 1 data* H'FF command H'D1 command 0 data* H'FF command H'D1 command 1 data* Command other than H'FF and H'D1 H'D1 command 0 data* Command other than H'FF and H'D1 H'D1 command Command other than H'D1 H'D1 command...
Page 435 15.4.4 Host Interface Shutdown Function (LPCPD) The host interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of host interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the software shutdown state is controlled by the SDWNB bit.
Page 436: Table 15.5 Scope Of Host Interface Pin Shutdown
Table 15.5 shows the scope of the host interface pin shutdown. Table 15.5 Scope of Host Interface Pin Shutdown Abbreviation Port LAD3 to LAD0 P33–P30 LFRAME LRESET LCLK SERIRQ LSCI LSMI GA20 CLKRUN LPCPD [Legend] Pin that is shutdown by the shutdown function ∆: Pin that is shutdown only when the LPC function is selected by register setting ×:...
Page 437: Host Interface Shutdown Function (Lpcpd)
The scope of the initialization in each mode is shown in table 15.6. Table 15.6 Scope of Initialization in Each Host Interface Mode Items Initialized LPC transfer cycle sequencer (internal state), LPCBSY and ABRT flags SERIRQ transfer cycle sequencer (internal state), CLKREQ and IRQBSY flags Host interface flags (IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1, C/D2, C/D3, OBF1,...
Page 438: Figure 15.5 Power-Down State Termination Timing
Figure 15.5 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3–LAD0 LFRAME At least 30 µs LRESET Figure 15.5 Power-Down State Termination Timing Rev. 1.00, 05/04, page 404 of 544 At least 100 µs At least 60 µs...
Page 439: Figure 15.6 Serirq Timing
15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt.
Page 440 Serial Interrupt Transfer Cycle Frame Drive Count Contents Source Start Slave Host IRQ0 Slave IRQ1 Slave Slave IRQ3 Slave IRQ4 Slave IRQ5 Slave IRQ6 Slave IRQ7 Slave IRQ8 Slave IRQ9 Slave IRQ10 Slave IRQ11 Slave IRQ12 Slave IRQ13 Slave IRQ14 Slave IRQ15 Slave...
Page 441: Host Interface Serialized Interrupt Operation (Serirq)
15.4.6 Host Interface Clock Start Request (CLKRUN) A request to restart the clock (LCLK) can be sent to the host processor by means of the CLKRUN pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host.
Page 442: Table 15.7 Receive Complete Interrupts And Error Interrupt
15.5 Interrupt Sources 15.5.1 IBFI1, IBFI2, IBFI3, and ERRI The host interface has four interrupt requests for the slave processor (this LSI): IBF1, IBF2, IBF3, and ERRI. IBFI1, IBFI2, and IBFI3 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively.
Page 443: Host Interface Clock Start Request (Clkrun)
Table 15.8 summarizes the methods of setting and clearing these bits, and figure 15.8 shows the processing flowchart. Table 15.8 HIRQ Setting and Clearing Conditions Host Interrupt Setting Condition HIRQ1 Internal CPU writes to ODR1, then reads 0 (independent from bit IRQ1E1 and writes 1 from IEDIR) HIRQ12 Internal CPU writes to ODR1, then reads 0...
Page 444: Interrupt Sources
ODR1 write Write 1 to IRQ1E1 OBF1 = 0? All bytes transferred? Figure 15.8 HIRQ Flowchart (Example of Channel 1) Rev. 1.00, 05/04, page 410 of 544 Slave CPU SERIRQ IRQ1 output SERIRQ IRQ1 source clearance Master CPU Interrupt initiation ODR1 read Hardware operation Software operation...
Page 445 15.6 Usage Notes 15.6.1 Module Stop Mode Setting LPC operation can be enabled or disabled using the module stop control register. The initial setting is for LPC operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 20, Power-Down Modes. 15.6.2 Notes on Using Host Interface The host interface provides buffering of asynchronous data from the host processor and slave...
Page 446 Table 15.9 Host Address Example Register Host Address when LADR3 = H'A24F IDR3 H'A24A and H'A24E ODR3 H'A24A STR3 H'A24E TWR0MW H'A250 TWR0SW H'A250 TWR1 H'A251 TWR2 H'A252 TWR3 H'A253 TWR4 H'A254 TWR5 H'A255 TWR6 H'A256 TWR7 H'A257 TWR8 H'A258 TWR9 H'A259 TWR10...
Page 447: Usage Notes
Section 16 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to six analog input channels to be selected. A/D conversion for digital input is effective as a comparator in multiple input testing. 16.1 Features • 10-bit resolution •...
Page 448: Figure 16.1 Block Diagram Of A/D Converter
A block diagram of the A/D converter is shown in figure 16.1. 10-bit D/A Sample-and-hold circuit ADTRG [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Figure 16.1 Block Diagram of A/D Converter Rev.
Page 449: Input/Output Pins
16.2 Input/Output Pins Table 16.1 summarizes the pins used by the A/D converter. The 6 analog input pins are divided into two groups consisting of four channels and two channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 and 5 (AN4 and AN5) comprising group 1. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter.
Page 450: Register Descriptions
16.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D control/status register (ADCSR) • A/D control register (ADCR) 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of...
Page 451: A/D Control/Status Register (Adcsr)
16.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Initial Bit Name Value ADIE ADST SCAN Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] • When A/D conversion ends in single mode •...
Page 452: A/D Control Register (Adcr)
Initial Bit Name Value Note: Only 0 can be written for clearing the flag. 16.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Initial Bit Name Value TRGS1 TRGS0 5 to 0 — All 1 Rev.
Page 453: Operation
16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion.
Page 454: Figure 16.2 Example Of A/D Converter Operation (Scan Mode, Channels An0 To An2 Selected)
Figure 16.2 shows the operation timing. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2.
Page 455: Input Sampling And A/D Conversion Time
16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t 1, then starts A/D conversion. Figure 16.3 shows the A/D conversion timing. Table 16.3 indicates the A/D conversion time.
Page 456: External Trigger Input Timing
Table 16.3 A/D Conversion Time (Single Mode) Item A/D conversion start delay time Input sampling time A/D conversion time Note: Values in the table indicate the number of states. 16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, external trigger input is enabled at the ADTRG pin.
Page 457: Interrupt Sources
16.5 Interrupt Sources The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1 after A/D conversion is completed. 16.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below.
Page 458: Figure 16.5 A/D Conversion Accuracy Definitions
Digital output H'3FF H'3FE H'3FD H'004 H'003 H'002 H'001 H'000 Figure 16.5 A/D Conversion Accuracy Definitions Digital output Figure 16.6 A/D Conversion Accuracy Definitions Rev. 1.00, 05/04, page 424 of 544 Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024...
Page 459: Usage Notes
16.7 Usage Notes 16.7.1 Permissible Signal Source Impedance This LSI's analog input (3-V version) is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 460: Setting Range Of Analog Power Supply And Other Pins
16.7.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of this LSI may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤...
Page 461: Module Stop Mode Setting
Notes: Values are reference values. 10 µF 2. R in : Input impedance Figure 16.8 Example of Analog Input Protection Circuit Note: * Values are reference values. Figure 16.9 Equivalent Circuit of Analog Input Pin 16.7.6 Module Stop Mode Setting A/D converter operation can be enabled or disabled using the module stop control register.
Page 462 Rev. 1.00, 05/04, page 428 of 544...
Page 463: Section 17 Ram
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR). Product Classification Flash memory version H8S/2111B-B 2 Kbytes H8S/2111B-C 3 Kbytes Section 17 RAM RAM Capacitance RAM Address...
Page 464 Rev. 1.00, 05/04, page 430 of 544...
Page 465: Section 18 Rom
18.1 Features • Size Product Classification H8S/2111B • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows:  8 Kbytes × 2 blocks, 16 Kbytes × 1 block, 28 Kbytes × 1 block, and 1 Kbyte × 4 blocks To erase the entire flash memory, each block must be erased in turn.
Page 466: Figure 18.1 Block Diagram Of Flash Memory
• Programmer mode In addition to on-board programming mode, programmer mode is supported to program or erase the flash memory using a PROM programmer. FLMCR1 FLMCR2 EBR1 EBR2 [Legend] FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2:...
Page 467: Mode Transitions
18.2 Mode Transitions When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 18.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program, and programmer modes are provided as modes to write and erase the flash memory.
Page 468: Figure 18.3 Boot Mode
1. Initial state The flash memory is erased at shipment. The following describes how to write over an old-version application program or data in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. <Host>...
Page 469: Figure 18.4 User Program Mode (Example)
1. Initial state (1) The program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. <Host>...
Page 470: Block Configuration
18.3 Block Configuration Figure 18.5 shows the block configuration of flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 8 Kbytes (2 blocks), 16 Kbytes (1 block), 28 Kbytes (1 block), and 1 Kbyte (4 blocks).
Page 471: Input/Output Pins
18.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 18.2. Table 18.2 Pin Configuration Pin Name Input Input Input Input Input Input TxD1 Output RxD1 Input 18.5 Register Descriptions The flash memory has the following registers. To access FLMCR1, FLMCR2, EBR1, or EBR2, the FLSHE bit in the serial/timer control register (STCR) should be set to 1.
Page 472: Flash Memory Control Register 1 (Flmcr1)
18.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1, used together with FLMCR2, makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 18.8, Flash Memory Programming/Erasing.FLMCR1 is initialized to H'80 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode.
Page 473: Flash Memory Control Register 2 (Flmcr2)
18.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 monitors the state of flash memory programming/erasing protection (error protection) and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0.
Page 474: Erase Block Registers 1 And 2 (Ebr1, Ebr2)
18.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) EBR1 and EBR2 are used to specify the flash memory erase block. EBR1 and EBR2 are initialized to H'00 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0.
Page 475: Operating Modes
18.6 Operating Modes The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses are connected to the lower 8 bits.
Page 476: Boot Mode
18.7.1 Boot Mode Table 18.5 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 18.8, Flash Memory Programming/Erasing.
Page 477: Table 18.5 Boot Mode Operation
7. Boot mode can be cleared by a reset. Cancel the reset* at least 20 states, and then setting the mode pins. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the mode pin input levels in boot mode. 9.
Page 478: Figure 18.6 On-Chip Ram Area In Boot Mode
Table 18.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19200 bps 8 to 10 MHz 9600 bps 4 to 10 MHz 4800 bps 4 to 10 MHz Notes: 1.
Page 479: User Program Mode
18.7.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program which provides the user program/erase control program from external memory.
Page 480: Flash Memory Programming/Erasing
18.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 and FLMCR2 settings, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode.
Page 481: Figure 18.9 Program/Program-Verify Flowchart
Write pulse application subroutine Sub-Routine Write Pulse WDT enable Set PSU bit in FLMCR2 Wait (γ) µs Set P bit in FLMCR1 Wait (z1) µs, (z2) µs or (z3) µs Clear P bit in FLMCR1 Wait (α) µs Clear PSU bit in FLMCR2 Wait (β) µs Disable WDT End Sub...
Page 482: Erase/Erase-Verify
18.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 18.10 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-block specification in erase block registers 1 and 2 (EBR1 and EBR2).
Page 483: Figure 18.10 Erase/Erase-Verify Flowchart
Set SWE bit in FLMCR1 Wait (x) µs Set EBR1 and EBR2 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs Set E bit in FLMCR1 Wait (z) ms Clear E bit in FLMCR1 Wait (α) µs Clear ESU bit in FLMCR2 Wait (β) µs Disable WDT Set EV bit in FLMCR1...
Page 484: Program/Erase Protection
18.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 18.9.1 Hardware Protection Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled or aborted by a reset (including WDT overflow reset), or a transition to hardware standby mode, software standby mode, sub-active mode, sub-sleep mode or watch mode.
Page 485: Interrupts During Flash Memory Programming/Erasing
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be entered by setting the P or E bit to 1. However, because the PV and EV bit settings are retained, a transition to verify mode can be made.
Page 486: Programmer Mode
In programmer mode, the on-chip flash memory can be programmed/erased by a PROM programmer via a socket adapter, just like for a discrete flash memory. Use a PROM programmer that supports the Renesas 64-Kbyte flash memory on-chip MCU device*. Figure 18.11 shows a memory map in programmer mode.
Page 487: Usage Notes
If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a PROM programmer that supports the Renesas 64-Kbyte flash memory on-chip MCU device at 3.3 V. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V.
Page 488 Rev. 1.00, 05/04, page 454 of 544...
Page 489: Section 19 Clock Pulse Generator
Section 19 Clock Pulse Generator This LSI incorporates a clock pulse generator, which generates the system clock (φ), bus master clock, and internal clock. The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform forming circuit.
Page 490: Oscillator
19.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator, or by providing external clock input. 19.1.1 Connecting Crystal Resonator Figure 19.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance R , given in table 19.1, should be used. An AT-cut parallel-resonance crystal resonator should be used.
Page 491: External Clock Input Method
19.1.2 External Clock Input Method Figure 19.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode.
Page 492: Figure 19.5 External Clock Input Timing
Table 19.3 External Clock Input Conditions Item Symbol External clock input pulse width low level External clock input pulse width high level External clock rising time External clock falling time Clock pulse width low level t Clock pulse width high level EXTAL Figure 19.5 External Clock Input Timing...
Page 493: Duty Correction Circuit
3.0 V STBY EXTAL φ (Internal and external) Note: * The external clock output stabilization delay time (t Figure 19.6 Timing of External Clock Output Stabilization Delay Time 19.2 Duty Correction Circuit The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects the duty of a clock that is output from the oscillator, and generates the system clock (φ).
Page 494: Subclock Input Circuit
19.5 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1. Subclock input conditions are shown in table 19.5.
Page 495: Clock Select Circuit
19.7 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI. A clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a system clock when returning from high-speed mode, medium-speed mode, sleep mode, reset state, or standby mode.
Page 496 Rev. 1.00, 05/04, page 462 of 544...
Page 497: Section 20 Power-Down Modes
Section 20 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules.
Page 498: Standby Control Register (Sbycr)
20.1.1 Standby Control Register (SBYCR) SBYCR controls power-down modes. Initial Bit Name Value SSBY STS2 STS1 STS0  SCK2 SCK1 SCK0 [Legend] Don't care Rev. 1.00, 05/04, page 464 of 544 Description Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction.
Page 499: Low-Power Control Register (Lpwrcr)
Table 20.1 Operating Frequency and Wait Time STS2 STS1 STS0 Wait Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved Reserved Shaded cells indicate the recommended specification. 20.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Initial Bit Name Value...
Page 500 Initial Bit Name Value LSON NESEL EXCLE   2 to 0 All 0 Rev. 1.00, 05/04, page 466 of 544 Description Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled.
Page 501: Module Stop Control Registers H And L (Mstpcrh, Mstpcrl)
20.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCRH and MSTPCRL specify on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. •...
Page 502: Mode Transitions And Lsi States
20.2 Mode Transitions and LSI States Figure 20.1 shows the enabled mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode.
Page 503: Table 20.2 Lsi Internal States In Each Operating Mode
Table 20.2 LSI Internal States in Each Operating Mode High- Medium- Function Speed Speed System clock pulse generator Functioning Functioning Subclock pulse generator Functioning Functioning Instruction Functioning Medium-speed execution operation Registers External Functioning Functioning interrupts IRQ0 to IRQ7 KIN0 to KIN15 WUE0 to WUE7 Peripheral WDT_1...
Page 504: Medium-Speed Mode
20.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32). On-chip peripheral modules other than the bus masters always operate on the system clock (φ).
Page 505: Sleep Mode
20.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do not stop.
Page 506: Figure 20.3 Application Example In Software Standby Mode
When the RES pin is driven low, system clock oscillation is started. At the same time as system clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high after clock oscillation stabilizes, the CPU begins reset exception handling.
Page 507: Hardware Standby Mode
20.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained.
Page 508: Watch Mode
20.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped.
Page 509: Subsleep Mode
20.8 Subsleep Mode The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. In subsleep mode, the CPU is stopped.
Page 510: Subactive Mode
20.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high- speed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode.
Page 511: Module Stop Mode
20.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the end of the bus cycle.
Page 512: Usage Notes
20.12 Usage Notes 20.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output.
Page 513: Section 21 List Of Registers
Section 21 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register Addresses (address order) •...
Page 514: Register Addresses (Address Order)
21.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Register Name Timer control register_B Timer control register_A Timer control/status register_B Timer control/status register_A...
Page 515 Register Name Bidirectional data register 1 Bidirectional data register 2 Bidirectional data register 3 Bidirectional data register 4 Bidirectional data register 5 Bidirectional data register 6 Bidirectional data register 7 Bidirectional data register 8 Bidirectional data register 9 Bidirectional data register 10 Bidirectional data register 11 Bidirectional data register 12 Bidirectional data register 13...
Page 516 Register Name Wakeup event interrupt mask register Port G output data register Port G input data register Port G data direction register Port E output data register Port F output data register Port E input data register Port E data direction register Port F input data register Port F data direction register Port C output data register...
Page 517 Register Name Keyboard control register H_1 Keyboard control register L_1 Keyboard data buffer register_1 Keyboard control register H_2 Keyboard control register L_2 Keyboard data buffer register_2 DDC switch register Interrupt control register A Interrupt control register B Interrupt control register C IRQ status register IRQ sense control register H IRQ sense control register L...
Page 518 Register Name Low power control register Module stop control register H Module stop control register L Serial mode register_1 C bus control register_1 Bit rate register_1 C bus status register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 C bus data register_1 Second slave address register_1...
Page 519 Register Name Output control register AFL Input capture register CH Output compare register DMH Input capture register CL Output compare register DML Input capture register DH Input capture register DL Timer control/status register_0 Timer counter_0 Timer counter_0 Port A output data register Port A input data register Port A data direction register Port 1 pull-up MOS control register...
Page 520 Register Name Port 8 data direction register Port 7 input data register Port B data direction register Port 8 data register Port 9 data direction register Port 9 data register Interrupt enable register Serial timer control register System control register Mode control register Bus control register Wait state control register...
Page 521 Register Name C bus mode register_0 Slave address register_0 A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Timer control/status register_1...
Page 522 Register Name Input capture register F Time constant register B_Y Timer counter_X Timer counter_Y Timer constant register C Timer input select register Timer constant register A_X Timer constant register B_X Timer connection register I Timer connection register S Note: The program development tool (emulator) does not support these registers. Rev.
Page 523: Register Bits
21.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers 8 bits, and 16-bit registers are shown as 2 lines. Register Abbreviation Bit 7 Bit 6 TCR_B CMIEB CMIEA TCR_A CMIEB CMIEA TCSR_B CMFB...
Page 524 Register Abbreviation Bit 7 Bit 6 TWR1 Bit 7 Bit 6 TWR2 Bit 7 Bit 6 TWR3 Bit 7 Bit 6 TWR4 Bit 7 Bit 6 TWR5 Bit 7 Bit 6 TWR6 Bit 7 Bit 6 TWR7 Bit 7 Bit 6 TWR8 Bit 7 Bit 6...
Page 525 Register Abbreviation Bit 7 Bit 6 WUEMRB WUEMR7 WUEMR6 PGODR PG7ODR PG6ODR PGPIN PG7PIN PG6PIN PGDDR PG7DDR PG6DDR PEODR PE7ODR PE6ODR PFODR PF7ODR PF6ODR PEPIN PE7PIN PE6PIN PEDDR PE7DDR PE6DDR PFPIN PF7PIN PF6PIN PFDDR PF7DDR PF6DDR PCODR PC7ODR PC6ODR PDODR PD7ODR PD6ODR PCPIN...
Page 526 Register Abbreviation Bit 7 Bit 6 ICRA ICRA7 ICRA6 ICRB ICRB7 ICRB6 ICRC ICRC7 ICRC6 IRQ7F IRQ6F ISCRH IRQ7SCB IRQ7SCA ISCRL IRQ3SCB IRQ3SCA ABRKCR — BARA BARB BARC FLMCR1 FLMCR2 FLER — PCSR — — EBR1 — — SYSCR2 — —...
Page 527 Register Abbreviation Bit 7 Bit 6 TIER ICIAE ICIBE TCSR ICFA ICFB FRCH Bit 15 Bit 14 FRCL Bit 7 Bit 6 OCRAH Bit 15 Bit 14 OCRBH Bit 15 Bit 14 OCRAL Bit 7 Bit 6 OCRBL Bit 7 Bit 6 IEDGA IEDGB...
Page 528 Register Abbreviation Bit 7 Bit 6 PAODR PA7ODR PA6ODR PAPIN PA7PIN PA6PIN PADDR PA7DDR PA6DDR P1PCR P17PCR P16PCR P2PCR P27PCR P26PCR P3PCR P37PCR P36PCR P1DDR P17DDR P16DDR P2DDR P27DDR P26DDR P1DR P17DR P16DR P2DR P27DR P26DR P3DDR P37DDR P36DDR P4DDR P47DDR P46DDR P3DR...
Page 529 Register Abbreviation Bit 7 Bit 6 TCR_0 CMIEB CMIEA TCR_1 CMIEB CMIEA TCSR_0 CMFB CMFA TCSR_1 CMFB CMFA TCORA_0 Bit 7 Bit 6 TCORA_1 Bit 7 Bit 6 TCORB_0 Bit 7 Bit 6 TCORB_1 Bit 7 Bit 6 TCNT_0 Bit 7 Bit 6 TCNT_1 Bit 7...
Page 530 Register Abbreviation Bit 7 Bit 6 TCR_X CMIEB CMIEA TCR_Y CMIEB CMIEA KMIMR KMIMR7 KMIMR6 TCSR_X CMFB CMFA TCSR_Y CMFB CMFA KMPCR KM7PCR KM6PCR TICRR Bit 7 Bit 6 TCORA_Y Bit 7 Bit 6 KMIMRA KMIMR15 KMIMR14 TICRF Bit 7 Bit 6 TCORB_Y Bit 7...
Page 531: Register States In Each Operating Mode
21.3 Register States in Each Operating Mode Register High-Speed/ Abbrevia- Medium- tion Reset Speed  Initialized TCR_B  Initialized TCR_A  Initialized TCSR_B  Initialized TCSR_A  Initialized TCORA_B  Initialized TCORA_A  Initialized TCORB_B  Initialized TCORB_A  Initialized TCNT_B ...
Page 532 Register High-Speed/ Abbrevia- Medium- tion Reset Speed — — TWR6 — — TWR7 — — TWR8 — — TWR9 — — TWR10 — — TWR11 — — TWR12 — — TWR13 — — TWR14 — — TWR15 — — IDR3 —...
Page 533 Register High-Speed/ Abbrevia- Medium- tion Reset Speed Initialized — WUEMRB Initialized — PGODR — — PGPIN Initialized — PGDDR Initialized — PEODR Initialized — PFODR — — PEPIN Initialized — PEDDR — — PFPIN Initialized — PFDDR Initialized — PCODR Initialized —...
Page 534 Register High-Speed/ Abbrevia- Medium- tion Reset Speed Initialized — ICRA Initialized — ICRB Initialized — ICRC Initialized — Initialized — ISCRH Initialized — ISCRL Initialized — ABRKCR Initialized — BARA Initialized — BARB Initialized — BARC Initialized — FLMCR1 Initialized —...
Page 535 Register High-Speed/ Abbrevia- Medium- tion Reset Speed Initialized — TIER Initialized — TCSR Initialized — FRCH Initialized — FRCL Initialized — OCRAH Initialized — OCRBH Initialized — OCRAL Initialized — OCRBL Initialized — Initialized — TOCR Initialized — ICRAH Initialized —...
Page 536 Register High-Speed/ Abbrevia- Medium- tion Reset Speed Initialized — PAODR — — PAPIN Initialized — PADDR Initialized — P1PCR Initialized — P2PCR Initialized — P3PCR Initialized — P1DDR Initialized — P2DDR Initialized — P1DR Initialized — P2DR Initialized — P3DDR Initialized —...
Page 537 Register High-Speed/ Abbrevia- Medium- tion Reset Speed Initialized — TCR_0 Initialized — TCR_1 Initialized — TCSR_0 Initialized — TCSR_1 Initialized — TCORA_0 Initialized — TCORA_1 Initialized — TCORB_0 Initialized — TCORB_1 Initialized — TCNT_0 Initialized — TCNT_1 Initialized — PWOERA Initialized —...
Page 538 High-Speed/ Register Medium- Abbrevia- Reset Speed tion Initialized — TCR_X Initialized — TCR_Y Initialized — KMIMR Initialized — TCSR_X Initialized — TCSR_Y Initialized — KMPCR Initialized — TICRR Initialized — TCORA_Y Initialized — KMIMRA Initialized — TICRF Initialized — TCORB_Y Initialized —...
Page 539: Register Select Conditions
21.4 Register Select Conditions Lower Address Register Name H'FE00 TCR_B H'FE01 TCR_A H'FE02 TCSR_B H'FE03 TCSR_A H'FE04 TCORA_B H'FE05 TCORA_A H'FE06 TCORB_B H'FE07 TCORB_A H'FE08 TCNT_B H'FE09 TCNT_A H'FE0A TISR_B H'FE0C TICRR_A H'FE0D TICRF_A H'FE0E TCRAB H'FE10 TCRXY* H'FE12 SPSR* H'FE14 PGCTL* H'FE16...
Page 540 Lower Address Register Name H'FE20 TWR0MW TWR0SW H'FE21 TWR1 H'FE22 TWR2 H'FE23 TWR3 H'FE24 TWR4 H'FE25 TWR5 H'FE26 TWR6 H'FE27 TWR7 H'FE28 TWR8 H'FE29 TWR9 H'FE2A TWR10 H'FE2B TWR11 H'FE2C TWR12 H'FE2D TWR13 H'FE2E TWR14 H'FE2F TWR15 H'FE30 IDR3 H'FE31 ODR3 H'FE32 STR3...
Page 541 Lower Address Register Name H'FE44 WUEMRB H'FE46 PGODR H'FE47 PGPIN (read) PGDDR (write) H'FE48 PEODR H'FE49 PFODR H'FE4A PEPIN (read) PEDDR (write) H'FE4B PFPIN (read) PFDDR (write) H'FE4C PCODR H'FE4D PDODR H'FE4E PCPIN (read) PCDDR (write) H'FE4F PDPIN (read) PDDDR (write) H'FED4 ICXR_0 H'FED5...
Page 542 Lower Address Register Name H'FEE8 ICRA H'FEE9 ICRB H'FEEA ICRC H'FEEB H'FEEC ISCRH H'FEED ISCRL H'FEF4 ABRKCR H'FEF5 BARA H'FEF6 BARB H'FEF7 BARC H'FF80 FLMCR1 H'FF81 FLMCR2 H'FF82 PCSR EBR1 H'FF83 SYSCR2 EBR2 H'FF84 SBYCR H'FF85 LPWRCR H'FF86 MSTPCRH H'FF87 MSTPCRL H'FF88 ICCR_1...
Page 543 Lower Address Register Name H'FF94 OCRAH OCRBH H'FF95 OCRAL OCRBL H'FF96 H'FF97 TOCR H'FF98 ICRAH OCRARH H'FF99 ICRAL OCRARL H'FF9A ICRBH OCRAFH H'FF9B ICRBL OCRAFL H'FF9C ICRCH OCRDMH H'FF9D ICRCL OCRDML H'FF9E ICRDH H'FF9F ICRDL H'FFA8 TCSR_0 TCNT_0 (write) H'FFA9 TCNT_0 (read) Register Select Condition MSTP13 = 0...
Page 544 Lower Address Register Name H'FFAA PAODR H'FFAB PAPIN (read) PADDR (write) H'FFAC P1PCR H'FFAD P2PCR H'FFAE P3PCR H'FFB0 P1DDR H'FFB1 P2DDR H'FFB2 P1DR H'FFB3 P2DR H'FFB4 P3DDR H'FFB5 P4DDR H'FFB6 P3DR H'FFB7 P4DR H'FFB8 P5DDR H'FFB9 P6DDR H'FFBA P5DR H'FFBB P6DR H'FFBC PBODR...
Page 545 Lower Address Register Name H'FFC8 TCR_0 H'FFC9 TCR_1 H'FFCA TCSR_0 H'FFCB TCSR_1 H'FFCC TCORA_0 H'FFCD TCORA_1 H'FFCE TCORB_0 H'FFCF TCORB_1 H'FFD0 TCNT_0 H'FFD1 TCNT_1 H'FFD3 PWOERA H'FFD5 PWDPRA H'FFD6 PWSL H'FFD7 PWDR0 to PWDR7 H'FFD8 ICCR_0 H'FFD9 ICSR_0 H'FFDE ICDR_0 SARX_0 H'FFDF ICMR_0...
Page 546 Lower Address Register Name H'FFEA TCSR_1 TCNT_1 (write) H’FFEB TCNT_1 (read) H'FFF0 TCR_X TCR_Y H'FFF1 KMIMR TCSR_X TCSR_Y H'FFF2 KMPCR TICRR TCORA_Y H'FFF3 KMIMRA TICRF TCORB_Y H'FFF4 TCNT_X TCNT_Y H'FFF5 TCORC TISR H'FFF6 TCORA_X H'FFF7 TCORB_X H'FFFC TCONRI H'FFFE TCONRS Note: The program development tool (emulator) does not support these registers.
Page 547: Section 22 Electrical Characteristics
Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 lists the absolute maximum ratings. Table 22.1 Absolute Maximum Ratings Item Power supply voltage I/O buffer power supply voltage Input voltage (except ports 7, A, P97, P86, P52, P42, and port G) Input Voltage (port A) Input voltage (P97, P86, P52, P42 and port G) Input voltage (port 7)
Page 548: Dc Characteristics
22.2 DC Characteristics Table 22.2 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 22.3 and 22.4, respectively. Table 22.2 DC Characteristics (1) Conditions: V = 3.0 V to 3.6 V* = 3.0 V to AV Item Schmitt P67 to...
Page 549 Item Output low All output pins (except RESO)* voltage Ports 1 to 3 RESO Notes: 1. Do not leave the AV Even if the A/D converter is not used, apply a value in the range 2.0 V to 3.6 V to AV and AV pins by connection to the power supply (V ≤...
Page 550: Table 22.2 Dc Characteristics (2)
Table 22.2 DC Characteristics (2) Conditions: V = 3.0 V to 3.6 V* = 3.0 V to AV Item Input leakage STBY, NMI, MD1, current Port 7 Three-state Ports 1 to 6, 8, 9, leakage , and B to G current (off state) Input pull-up...
Page 551: Table 22.2 Dc Characteristics (3) When Lpc Function Is Used
Item Analog power supply voltage* RAM standby voltage Notes: 1. Do not leave the AV Even if the A/D converter is not used, apply a value in the range 2.0 V to 3.6 V to AV and AV pins by connection to the power supply (V ≤...
Page 552: Figure 22.1 Darlington Pair Drive Circuit (Example)
Table 22.3 Permissible Output Currents Conditions: = 3.0 V to 3.6 V, V Item Permissible SCL1, SCL0, output SDA1, SDA0, low current PS2AC to PS2CC, (per pin) PS2AD to PS2CD, PA7 to PA4, ExSDAA, ExSCLA, ExSDAB, ExSCLB (bus drive function selected) Ports 1, 2, 3 RESO...
Page 553: Figure 22.2 Led Drive Circuit (Example)
Figure 22.2 LED Drive Circuit (Example) Table 22.4 Bus Drive Characteristics Conditions: = 3.0 V to 3.6 V, V Applicable Pins: SCL1, SCL0, SDA1, SDA0 ExSDAA, ExSCLA, ExSDAB, ExSCLB (bus drive function selected) Item Schmitt trigger input voltage Input high voltage Input low voltage Output low voltage Input capacitance...
Page 554: Ac Characteristics
Conditions: = 3.0 V to 3.6 V, V Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive function selected) Item Output low voltage 22.3 AC Characteristics Figure 22.3 shows the test conditions for the AC characteristics. Chip output pin Rev.
Page 555: Clock Timing
22.3.1 Clock Timing Table 22.5 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details on external clock input (EXTAL pin and EXCL pin) timing, see section19, Clock Pulse Generator.
Page 556: Control Signal Timing
22.3.2 Control Signal Timing Table 22.6 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 22.6 Control Signal Timing Conditions: V = 3.0 V to 3.6 V, V maximum operating frequency, T Item...
Page 557: Timing Of On-Chip Peripheral Modules
22.3.3 Timing of On-Chip Peripheral Modules Tables 22.7 to 22.10 show the on-chip peripheral module timing. The only on-chip peripheral modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and Table 22.7 Timing of On-Chip Peripheral Modules (1) Conditions: V = 3.0 V to 3.6 V, V...
Page 558: Table 22.8 Keyboard Buffer Controller Timing
Item Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) Trigger input setup time t converter RESO output delay time t RESO output pulse width Note: Only peripheral modules that can be used in subclock operation Table 22.8 Keyboard Buffer Controller Timing Conditions: V = 3.0 V to 3.6 V, V...
Page 559: Table 22.9 I 2 C Bus Timing
Table 22.9 I C Bus Timing Conditions: V = 3.0 V to 3.6 V, V = –20 to +75°C Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time...
Page 560: A/D Conversion Characteristics
Table 22.10 LPC Module Timing Conditions: V = 3.0 V to 3.6 V, V = –20 to +75°C Item Input clock cycle Input clock pulse width (H) t Input clock pulse width (L) t Transmit signal delay time t Transmit signal floating delay time Receive signal setup time Receive signal hold time...
Page 561: Flash Memory Characteristics
22.5 Flash Memory Characteristics Table 22.12 shows the flash memory characteristics. Table 22.12 Flash Memory Characteristics Conditions: = 3.0 V to 3.6 V, V Item Programming time* Erase time* Reprogramming count Programming Wait time after SWE-bit setting* Wait time after PSU-bit setting* Wait time after P-bit setting*...
Page 562 Item Erase Wait time after SWE-bit setting* Wait time after ESU-bit setting* Wait time after E-bit setting* Wait time after E-bit clear* Wait time after ESU-bit clear* Wait time after EV-bit setting* Wait time after dummy write* Wait time after EV-bit clear* Wait time after SWE-bit clear*...
Page 563: Usage Note
22.6 Usage Note The method of connecting an external capacitor is shown in figure 22.4. Connect the system power supply to the VCL pin together with the VCC pins. Bypass capacitor 10 µF < Vcc = 3.0 V to 3.6 V > Connect the Vcc power supply to the chip's VCL pin in the same way as the VCC pins.
Page 564: Figure 22.6 Oscillation Settling Timing
EXTAL DEXT V CC STBY OSC1 φ Figure 22.6 Oscillation Settling Timing φ IRQi (i = 0, 1, 2, 6, 7) Figure 22.7 Oscillation Setting Timing (Exiting Software Standby Mode) Rev. 1.00, 05/04, page 530 of 544 DEXT OSC1 OSC2...
Page 565: Control Signal Timing
22.7.2 Control Signal Timing The control signal timings are shown below. φ φ IRQi (i = 7 to 0) IRQi Edge input (i = 7 to 0) IRQi Level input (i = 7 to 0) RESS RESW Figure 22.8 Reset Input Timing NMIS NMIW IRQW...
Page 566: On-Chip Peripheral Module Timing
22.7.3 On-Chip Peripheral Module Timing The on-chip peripheral module timings are shown below. φ Ports 1 to 9, and A to G (read) Ports 1 to 6, 8, 9, and A to G (write) Figure 22.10 I/O Port Input/Output Timing φ...
Page 567: Figure 22.13 8-Bit Timer Output Timing
φ TMO0, TMO1 TMOX, ExTMOX, TMOY, TMOA, TMOB Figure 22.13 8-Bit Timer Output Timing φ TMCI0, TMCI1 TMIX, TMIY, ExTMIX, ExTMIY, TMIA, TMIB Figure 22.14 8-Bit Timer Clock Input Timing φ TMRI0, TMRI1 TMIX, TMIY, ExTMIX, ExTMIY, TMIA, TMIB Figure 22.15 8-Bit Timer Reset Input Timing φ...
Page 568: Figure 22.17 Sck Clock Input Timing
SCK1, ExSCK1 Figure 22.17 SCK Clock Input Timing SCK1, ExSCK1 TxD1, ExTxD1 (transmit data) RxD1, ExRxD1 (receive data) Figure 22.18 SCI Input/Output Timing (Synchronous Mode) φ ADTRG Figure 22.19 A/D Converter External Trigger Input Timing φ RESO Figure 22.20 WDT Output Timing (RESO) Rev.
Page 569: Figure 22.21 Keyboard Buffer Controller Timing
1. Reception φ KCLK/KD * 2. Transmission (a) φ KCLK/KD * Transmission (b) KCLK/KD * φ shown here is the clock scaled by 1/N when the operating mode is active Note: medium-speed mode. * KCLK: PS2AC to PS2CC PS2AD to PS2CD Figure 22.21 Keyboard Buffer Controller Timing SDA0, SDA1,...
Page 570: Figure 22.23 Host Interface (Lpc) Timing
LCKH Lcyc LCLK LCKL LCLK LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) LAD3 to LAD0, SERIRQ, CLKRUN LFRAME (Receive signal) LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) Figure 22.23 Host Interface (LPC) Timing Testing voltage: 0.4Vcc 50pF Figure 22.24 Tester Measurement Condition Rev.
Page 571: Appendix
I/O Port States in Each Processing State Table A.1 I/O Port States in Each Processing State Hardware Port Name Standby Pin Name Reset Mode Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 97 Port 96 φ...
Page 572: Product Codes
Product Codes Product Type H8S/2111B-B Flash memory version (3 V version) H8S/2111B-C Rev. 1.00, 05/04, page 538 of 544 Product Code Mark Code HD64F2111BVB F2111BVTE10B HD64F2111BVC F2111BVTE10C Package (Package Code) 144-pin TQFP (TFP-144)
Page 573: Package Dimensions
Package Dimensions For package dimensions, dimensions described in Renesas Semiconductor Packages Data Book have priority. 18.0 ± 0.2 0.18 ± 0.05 0.16 ± 0.04 0.08 *Dimension including the plating thickness Base material dimension Figure C.1 Package Dimensions (TFP-144) 0.07 M...
Page 574 Rev. 1.00, 05/04, page 540 of 544...
Page 575: Index
16-bit count mode... 210 16-bit free-running timer (FRT) ... 157 8-bit PWM timer (PWM)... 147 8-bit timer (TMR) ... 183 A/D converter ... 413 A20 gate... 398 Absolute address... 41 Additional pulse... 154 Address map ... 57 Address space ... 20 Addressing modes...
Page 576 ICIX... 215 IICI ... 337 Immediate ... 42 Increment timing ... 170 Input capture input... 172 Input capture operation... 212 Instruction set ... 29 Interrupt control modes ... 80 Interrupt controller... 67 Interrupt exception handling... 63 Interrupt Exception handling vector table 78 Interrupt mask bit ...
Page 577 ICXR...302, 482, 491, 499, 507 IDR ...380, 481, 490, 498, 506 IER...73, 486, 494, 502, 510 ISCR ...72, 483, 492, 500, 508 ISR...73, 483, 492, 500, 508 KBBR ...354, 482, 491, 499, 507 KBCR ...351, 482, 491, 499, 507 KMIMR ...73, 487, 496, 504, 512 KMIMRA ...73, 487, 496, 504, 512 KMPCR ...113, 487, 496, 504, 512 LADR3 ...379, 481, 490, 498, 506...
Page 578 TCONRI ...203, 488, 496, 504, 512 TCONRS ...203, 488, 496, 504, 512 TCOR ...191, 486, 495, 503, 511 TCORC...202, 488, 496, 504, 512 TCR ...166, 192, 484, 486, 493, ...495, 501, 503, 509, 511 TCRAB... 205 TCRXY ... 204 TCSR ...163, 196, 224, 484, 485, ...486, 493, 495, 501, 503, ...
Page 579 Hardware Manual H8S/2111B Publication Date: Rev.1.00, May 14, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd..  2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 580 Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd.
Page 582 H8S/2111B Hardware Manual...

This manual is also suitable for:

Hd64f2111b

Renesas H8S/2111B Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller (BSC)

Section 7 I/O Ports

Section 8 8-Bit PWM Timer (PWM)

Section 9 16-Bit Free-Running Timer (FRT)

Quick Links

Related Manuals for Renesas H8S/2111B

Summary of Contents for Renesas H8S/2111B