Renesas Hitachi H8S/2194 Series Hardware Manual page 826

(2) Horizontal Sync Signal Threshold Register (HTR)
7
Bit :
—
Initial value :
1
R/W : —
Sets the threshold for the horizontal sync signal when the signal is detected from the
composite sync signal. The threshold is set by bits 3 to 0 (HTR3 to HTR0). Bits 7 and 4 are
reserved.
HTR is an 8-bit write-only register. If a read is attempted, an undetermined value is read
out. It is initialized to H'F0 by a reset, stand-by or module stop.
Figure 28.73 shows threshold and separated sync signals.
Hpuls
Csync
Counter value
H'00
SEPH
SEPV
[Legend]
TH : Cycle of the horizontal sync signal (NTSC: 63.6, PAL: 64 [ s])
Hpuls : Pulse width of the horizontal sync signal (NTSC, PAL: 4.7 [ s])
VVTH : Value set as the threshold of the vertical sync signal
HVTH : Value set as the threshold of the horizontal sync signal
SEPV : Detected vertical sync signal
SEPH : Detected horizontal sync signal (before supplement)
Figure 28.73 Threshold and Separated Sync Signals
6 5
— —
1 1
— —
1/2 Hpuls
TH
VVTH
HVTH
4 3 2
HTR3 HTR2
—
1 0 0
—
W W
Hpuls
TH
VD interrupt
Rev. 2.0, 11/00, page 799 of 1037
1 0
HTR1 HTR0
0 0
W W