Register Descriptions; Software-Triggered A/D Result Register (Adr); Hardware-Triggered A/D Result Register (Ahr) - Renesas Hitachi H8S/2194 Series Hardware Manual

26.2

Register Descriptions

26.2.1

Software-Triggered A/D Result Register (ADR)

Bit : 15 14
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Initial value :
0 0
R/W : R R
The software-triggered A/D result register (ADR) is a register that stores the result of an A/D
conversion started by software.
The A/D-converted data is 10-bit data. Upon completion of software-triggered A/D conversion,
the 10-bit result data is transferred to ADR and the data is retained until the next software-
triggered A/D conversion completion. The upper 8 bits of the data are stored in the upper bytes
(bits 15 to 8) of ADR, and the lower 2 bits are stored in the lower bytes (bits 7 and 6). Bits 5 to
0 are always read as 0.
ADR can be read by the CPU at any time, but the ADR value during A/D conversion is not
fixed. The upper bytes can always be read directly, but the data in the lower bytes is transferred
via a temporary register (TEMP). For details, see section 26.3, Interface to Bus Master.
ADR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop
mode, standby mode, watch mode, subactive mode and subsleep mode.
26.2.2

Hardware-Triggered A/D Result Register (AHR)

15 14
Bit :
AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 AHR1 AHR0
0 0
Initial value :
R/W : R R
The hardware-triggered A/D result register (AHR) is a register that stores the result of an A/D
conversion started by hardware (internal signal: ADTRG and DFG) or by external trigger input
$'75*
( ).
The A/D-converted data is 10-bit data. Upon completion of hardware- or external-triggered A/D
conversion, the 10-bit result data is transferred to AHR and the data is retained until the next
hardware- or external- triggered A/D conversion completion. The upper 8 bits of the data are
stored in the upper bytes (bits 15 to 8) of AHR, and the lower 2 bits are stored in the lower bytes
(bits 7 and 6). Bits 5 to 0 are always read as 0.
ADRH
13 12 11 10
0 0 0 0
R R R R
AHRH
13 12 11 10
0 0 0 0
R R R R
9 8 7 6
0 0 0 0
R R R R
9 8 7 6
0 0 0 0
R R R R
Rev. 2.0, 11/00, page 577 of 1037
ADRL
5 4 3 2
— — — —
0 0 0 0
— — — —
AHRL
5 4 3 2
— — — —
0 0 0 0
— — — —
1 0
— —
0 0
— —
1 0
— —
0 0
— —