Interrupt Operation; Interrupt Control Modes And Interrupt Operation - Renesas Hitachi H8S/2194 Series Hardware Manual

6.4

Interrupt Operation

6.4.1

Interrupt Control Modes and Interrupt Operation

Interrupt operations in this LSI differ depending on the interrupt control mode.
NMI interrupts and address trap interrupts are accepted at all times except in the reset state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided
for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request.
Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 6.5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated
by the I and UI bits in the CPU's CCR.
Table 6.5 Interrupt Control Modes
Interrupt SYSCR
Control
Mode INTM1
0 0
1
Figure 6.4 shows a block diagram of the priority decision circuit.
Interrupt source
Interrupt control modes 0 and 1
Figure 6.4 Block Diagram of Interrupt Priority Determination Operation
Priority Setting
INTM0 Register
0 ICR
1 ICR
I C R
I UI
Interrupt acceptance
control and 3-level
mask control
Interrupt
Mask Bits Description
I Interrupt mask control is
performed by the I bit
Priority can be set with ICR
I, UI 3-level interrupt mask control is
performed by the I and UI bits
Priority can be set with ICR
Default priority
determination
Rev. 2.0, 11/00, page 111 of 1037
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