Renesas Hitachi H8S/2194 Series Hardware Manual page 567

2
Bit 5: I C Bus Interface Continuous Transmission/Reception Interrupt Request Flag
(IRTR)
2
Indicates that the I C bus interface has issued an interrupt request to the CPU, and the source is
completion of reception/transmission of one frame in continuous transmission/reception for
which DTC* activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1
at the same time.
IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by
reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared
automatically when the IRIC flag is cleared to 0.
Note: * This LSI does not incorporate DTC.
Bit 5
IRTR Description
0 Waiting for transfer, or transfer in progress
[Clearing condition]
(1) When 0 is written in IRTR after reading IRTR = 1
(2) When the IRIC flag is cleared to 0
1 Continuous transfer state
[Setting condition]
T
2
In I C bus interface slave mode
• When the TDRE or RDRF flag is set to 1 when AASX = 1
T
In other modes
• When the TDRE or RDRF flag is set to 1
Rev. 2.0, 11/00, page 540 of 1037
(Initial value)