Renesas Hitachi H8S/2194 Series Hardware Manual page 501

Start
bit
1
0 D0
TDRE
TEND
TXI interrupt Data written to TDR1 and
request TDRE flag cleared to 0
generated in TXI interrupt handling
routine
Figure 23.6 Example of Operation in Transmission in Asynchronous Mode
Rev. 2.0, 11/00, page 474 of 1037
Data
Parity Stop
bit bit
D1 D7 0/1
TXI interrupt request
generated
1 frame
(Example with 8-Bit Data, Parity, One Stop Bit)
Data
Start
bit
1 0 D0 D1
Parity Stop
bit bit
1
Idle state
D7 0/1 1
(mark state)
TEI interrupt request
generated