Slave Receive Operation - Renesas Hitachi H8S/2194 Series Hardware Manual

25.3.4

Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The receive procedure and operations in slave
receive mode are described below.
[1] Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according
to the operating mode.
[2] A start condition output by the master device sets the BBSY flag to 1 in ICCR.
[3] After the slave device detects the start condition, if the first frame matches its slave address,
it functions as the slave device designated as the master device. If the 8th bit data (R/
0, TRS bit in ICCR remains 0 and executes slave receive operation.
[4] At the ninth clock pulse of the receive frame, the slave device drives SDA low to
acknowledge the transfer. At the same time, the IRIC flag is set to 1 in ICCR. If IEIC is 1 in
ICCR, a CPU interrupt is requested. If the RDRF internal flag is 0, it is set to 1 and
continuous reception is performed. If the RDRF internal flag is 1, the slave device holds
SCL low from the fall of the receive clock until it has read the data in ICDR.
[5] Read ICDR and clear IRIC to 0 in ICCR. At this time, the RDFR flag is cleared to 0.
Steps [4] and [5] can be repeated to receive data continuously. When a stop condition is
detected (a low-to-high transition of SDA while SCL is high), the BBSY flag is cleared to 0 in
ICCR.
Rev. 2.0, 11/00, page 553 of 1037
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