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(10) FIFO Timer Capture Register (FTCTR)
15
Bit :
FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8 FTCTR7 FTCTR6 FTCTR5 FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0
Initial value :
0
R
R/W :
FTCTR is a register to display the count of the 16-bit timer counter.
FTCTR is a 16-bit read-only register. It stores the counter value if a VD signal was detected in
PB mode. Only a word access is accepted. If a byte access is attempted, resulting operation is
not assured. It is initialized to H'0000 by a reset or stand-by.
Note: Its address is shared with the FIFO timing pattern register 1 (FTPRA). Accordingly, if a
write is attempted, the value is written in FTPRA.
(11) DFG Reference Count Register (DFCTR)
Bit :
7
—
Initial value :
1
—
R/W :
DFCTR is a register to count the DFG pulses.
DFCTR is an 8-bit read-only register. Bits 7 to 5 are reserved. If a read is attempted, 1 is read
out. It is initialized to H'E0 by a reset or stand-by.
Note: Its address is shared with the DFG reference register 1 (DFCRA). Accordingly, if a
write is attempted, the value is written in DFCRA.
Bits 4 to 0: DFG Pulse Count Bits (DFCTR4 to DFCTR0)
Count the number of pulses of DFG.
Rev. 2.0, 11/00, page 668 of 1037
14
13
12
11
10
0
0
0
0
0
R
R
R
R
R
6
5
—
—
1
1
—
—
9
8
7
6
5
0
0
0
0
0
R
R
R
R
R
4
3
DFCTR4
DFCTR3
DFCTR2
0
0
R
R
4
3
2
1
0
0
0
0
0
0
R
R
R
R
R
2
1
0
DFCTR1
DFCTR0
0
0
0
R
R
R
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