Register Configuration - Renesas Hitachi H8S/2194 Series Hardware Manual

26.1.4

Register Configuration

Table 26.2 summarizes the registers of the A/D converter.
Table 26.2 A/D Converter Registers
Name
Software trigger A/D
result register H
Software trigger A/D
result register L
Hardware trigger A/D
result register H
Hardware trigger A/D
result register L
A/D control register
A/D control/status
register
A/D trigger selection
register
Port mode register 0
Notes: 1. Only 0 can be written in bits 7 and 6, to clear the flag. Bits 3 to 1 are read-only.
2. Lower 16 bits of the address.
Rev. 2.0, 11/00, page 576 of 1037
Abbrev. R/W
ADRH R
ADRL R
AHRH R
AHRL R
ADCR R/W
*1
ADCSR R (W)
ADTSR R/W
PMR0 R/W
Size Initial Value
Byte H'00
Byte H'00
Byte H'00
Byte H'00
Byte H'40
Byte H'01
Byte H'FC
Byte H'00
*2
Address
H'D130
H'D131
H'D132
H'D133
H'D134
H'D135
H'D136
H'FFCD