Renesas Hitachi H8S/2194 Series Hardware Manual page 483

Bit 3: Parity Error (PER)
Indicates that a parity error occurred during reception using parity addition in asynchronous
mode, causing abnormal termination.
Bit 4
PER Description
0 [Clearing conditions]
When 0 is written in PER after reading PER = 1
1 [Setting conditions]
When, in reception, the number of 1 bits in the receive data plus the parity bit does
not match the parity setting (even or odd) specified by the O/
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR1 is
cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR1 but the RDRF flag is
not set. Also, subsequent serial reception cannot be continued while the PER flag is
set to 1. In clock synchronous mode, serial transmission cannot be continued, either.
Bit 2: Transmit End (TEND)
Indicates that there is no valid data in TDR1 when the last bit of the transmit character is sent,
and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2
TEND Description
0 [Clearing conditions]
When 0 is written in TDRE after reading TDRE = 1
1 [Setting conditions]
(1) When the TE bit in SCR1 is 0
(2) When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit
character
Rev. 2.0, 11/00, page 456 of 1037
(Initial value)
*2
bit in SMR1
(Initial value)
*1