Renesas Hitachi H8S/2194 Series Hardware Manual page 19

16.5.2 Reeling Controls.............................................................................................. 352
16.5.3 Slow Tracking Mono-multi Function ............................................................... 352
16.5.4 Acceleration and Braking Processes of the Capstan Motor................................ 353
Section 17 Timer X1...................................................................................... 355
17.1 Overview..................................................................................................................... 355
17.1.1 Features........................................................................................................... 355
17.1.2 Block Diagram ................................................................................................ 356
17.1.3 Pin Configuration ............................................................................................ 357
17.1.4 Register Configuration..................................................................................... 358
17.2 Descriptions of Respective Registers ............................................................................ 359
17.2.1 Free Running Counter (FRC)........................................................................... 359
17.2.2 Output Comparing Register A and B (OCRA and OCRB) ................................ 360
17.2.3 Input Capture Register A Through D (ICRA Through ICRD) ........................... 361
17.2.4 Timer Interrupt Enabling Register (TIER)........................................................ 363
17.2.5 Timer Control/Status Register X (TCSRX) ...................................................... 366
17.2.6 Timer Control Register X (TCRX)................................................................... 370
17.2.7 Timer Output Comparing Control Register (TOCR) ......................................... 372
17.2.8 Module Stop Control Register (MSTPCR) ....................................................... 375
17.3 Operation..................................................................................................................... 376
17.3.1 Operation of the Timer X1............................................................................... 376
17.3.2 Counting Timing of the FRC ........................................................................... 377
17.3.3 Output Comparing Signal Outputting Timing................................................... 378
17.3.4 FRC Clearing Timing ...................................................................................... 378
17.3.5 Input Capture Signal Inputting Timing............................................................. 379
17.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Timing ........................... 380
17.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing ....................... 381
17.3.8 Overflow Flag (CVF) Setting Up Timing ......................................................... 381
17.4 Operation Mode of the Timer X1 ................................................................................. 382
17.5 Interrupt Causes........................................................................................................... 383
17.6 Exemplary Uses of the Timer X1 ................................................................................. 384
17.7 Precautions when Using the Timer X1.......................................................................... 385
17.7.1 Competition between Writing and Clearing with the FRC ................................ 385
17.7.2 Competition between Writing and Counting Up with the FRC.......................... 386
17.7.3 Competition between Writing and Comparing Match with the OCR ................. 387
17.7.4 Changing Over the Internal Clocks and Counter Operations ............................. 388
Section 18 Watchdog Timer (WDT) .............................................................. 391
18.1 Overview..................................................................................................................... 391
18.1.1 Features........................................................................................................... 391
18.1.2 Block Diagram ................................................................................................ 392
18.1.3 Register Configuration..................................................................................... 393
18.2 Register Descriptions ................................................................................................... 394
Rev. 2.0, 11/00, page x of xviii