Low-Power Control Register (Lpwrcr) - Renesas Hitachi H8S/2194 Series Hardware Manual

4.2.2

Low-Power Control Register (LPWRCR)

Bit :
DTON
Initial value :
R/W : R/W
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a reset.
Bit 7: Direct-Transfer On Flag (DTON)
Specifies whether a direct transition is made between high-speed mode, medium-speed mode,
and subactive mode when making a power-down transition by executing a SLEEP instruction.
The operating mode to which the transition is made after SLEEP instruction execution is
determined by a combination of other control bits.
Bit 7
DTON Description
• When a SLEEP instruction is executed in high-speed mode or medium-speed
0
mode, a transition is made to sleep mode, standby mode, or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition is made
to subsleep mode or watch mode
• When a SLEEP instruction is executed in high-speed mode or medium-speed
1
mode, transition is made directly to subactive mode, or a transition is made to
sleep mode or standby mode
• When a SLEEP instruction is executed in subactive mode, a transition is made
directly to high-speed mode, or a transition is made to subsleep mode
Bit 6: Low-Speed On Flag (LSON)
Determines the operating mode in combination with other control bits when making a power-
down transition by executing a SLEEP instruction. Also controls whether a transition is made to
high-speed mode or to subactive mode when watch mode is cleared.
Rev. 2.0, 11/00, page 74 of 1037
7 6 5
LSON NESEL
0 0 0
R/W R/W
4 3 2
— — —
0 0 0
— — —
1 0
SA1 SA0
0 0
R/W R/W
(Initial value)