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H'D039: Drum Phase Error Detection Control Register DPGCR: Drum Error Detector
7
Bit :
DPCS1
0
Initial value :
R/W
R/W :
Clock source select bit
DPCS1 DPCS0
0
1
Note: * Only 0 can be written.
H'D03A: Specified Drum Phase Preset Data Register 2 DPPR2: Drum Error Detector
15
14
Bit :
Initial value :
0
0
R/W :
W
W
H'D03C: Specified Drum Phase Preset Data Register 1 DPPR1: Drum Error Detector
Bit :
7
—
Initial value :
1
—
R/W :
Rev. 2.0, 11/00, page 926 of 1037
6
5
DPCS0
DPOVF
0
0
R/(W) *
R/W
Error data latch signal select bit
0
HSW (VideoFF) signal
1
NHSW (NarrowFF) signal
Counter overflow flag
0
Normal status
1
Counter overflows.
Description
φs
0
φs/2
1
φs/3
0
φs/4
1
13
12
11
10
0
0
0
0
W
W
W
W
6
5
—
—
1
1
—
—
4
3
N/V
HSWES
0
0
R/W
R/W
Edge select bit
0
Latch at rising edge
1
Latch at falling edge
9
8
7
6
5
0
0
0
0
0
W
W
W
W
W
4
3
—
1
0
—
W
2
1
0
—
—
—
1
1
1
—
—
—
4
3
2
1
0
0
0
0
W
W
W
W
2
1
0
0
0
0
W
W
W
0
0
W
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