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(8) Duty I/O Register (DI/O)
Bit :
7
VCTR2
Initial value :
1
W
R/W :
Note: * Only 0 can be written.
The duty I/O register is an 8-bit register that confirms and determines the operating status of the
CTL circuit.
It is initialized to H'F1 by a reset, and in standby mode, module stop mode, and CTL stop mode.
Bits 7, 6, and 5: VISS Interrupt Setting Bits (VCTR2, VCTR1, VCTR0)
Combination of VCTR2, VCTR1 and VCTR0 sets number of 1 pulse detection in VISS
detection mode. Detecting the set number of pulse detection is considered as VISS detection,
and an interrupt request is generated.
Note: When changing the detection pulse number during VISS detection, initialize VISS first,
then resume the VISS detection setting.
Bit 7
Bit 6
VCTR2
VCTR1
0
0
1
1
0
1
Bit 4: Reserved
Writes are disabled. When read, undefined values are obtained.
6
5
VCTR1
VCTR0
1
1
W
W
Bit 5
VCTR0
Number of 1-pulse for Detection
0
2
1
4 (SYNC mark)
0
6
1
8 (mark A, short)
0
12 (mark A, long)
1
16
0
24 (mark B)
1
32
4
3
2
—
BPON
BPS
1
0
0
—
W
W
Rev. 2.0, 11/00, page 759 of 1037
1
0
BPF
DI/O
0
1
R/(W) *
R/W
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