Renesas Hitachi H8S/2194 Series Hardware Manual page 25

28.6.3 Register Configuration..................................................................................... 683
28.6.4 Register Descriptions....................................................................................... 684
28.6.5 Description of Operation ................................................................................. 689
28.6.6 f Correction in Trick Play Mode ..................................................................... 691
H
28.7 Drum Phase Error Detector .......................................................................................... 692
28.7.1 Overview ........................................................................................................ 692
28.7.2 Block Diagram ................................................................................................ 692
28.7.3 Register Configuration..................................................................................... 694
28.7.4 Register Descriptions....................................................................................... 695
28.7.5 Description of Operation ................................................................................. 698
28.7.6 Phase Comparison ........................................................................................... 700
28.8 Capstan Speed Error Detector ...................................................................................... 701
28.8.1 Overview ........................................................................................................ 701
28.8.2 Block Diagram ................................................................................................ 701
28.8.3 Register Configuration..................................................................................... 703
28.8.4 Register Descriptions....................................................................................... 704
28.8.5 Description of Operation ................................................................................. 708
28.9 Capstan Phase Error Detector....................................................................................... 710
28.9.1 Overview ........................................................................................................ 710
28.9.2 Block Diagram ................................................................................................ 710
28.9.3 Register Configuration..................................................................................... 712
28.9.4 Register Descriptions....................................................................................... 713
28.9.5 Description of Operation ................................................................................. 716
28.10 X-Value and Tracking Adjustment Circuit.................................................................... 718
28.10.1 Overview ........................................................................................................ 718
28.10.2 Block Diagram ................................................................................................ 718
28.10.3 Register Descriptions....................................................................................... 720
28.11 Digital Filters............................................................................................................... 723
28.11.1 Overview ........................................................................................................ 723
28.11.2 Block Diagram ................................................................................................ 724
28.11.3 Arithmetic Buffer ............................................................................................ 726
28.11.4 Register Configuration..................................................................................... 727
28.11.5 Register Descriptions....................................................................................... 728
28.11.6 Filter Characteristics........................................................................................ 736
28.11.7 Operations in Case of Transient Response........................................................ 738
28.11.8 Initialization of Z
28.12 Additional V Signal Generator ..................................................................................... 740
28.12.1 Overview ........................................................................................................ 740
28.12.2 Pin Configuration ............................................................................................ 741
28.12.3 Register Configuration..................................................................................... 741
28.12.4 Register Description ........................................................................................ 741
28.12.5 Additional V Pulse Signal................................................................................ 743
28.13 CTL Circuit ................................................................................................................. 746
Rev. 2.0, 11/00, page xvi of xviii
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