Section 5 Exception Handling; Overview; Exception Handling Types And Priority - Renesas Hitachi H8S/2194 Series Hardware Manual

5.1

Overview

5.1.1

Exception Handling Types and Priority

As table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 5.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Trap instruction
exceptions are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR.
Table 5.1 Exception Types and Priority
Exception
Priority Type
High Reset
*1
Trace
Interrupt
Direct transition
Trap instruction
*3
Low
(TRAPA)
Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. (They cannot be used in
this LSI.) Trace exception handling is not executed after execution of an RTE
instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in the program
execution state.

Section 5 Exception Handling

Start of Exception Handling
Starts immediately after a low-to-high transition at the
when the watchdog timer overflows
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued
Started by a direct transition resulting from execution of a SLEEP
instruction
Started by execution of a trap instruction (TRAPA)
# $
*2
Rev. 2.0, 11/00, page 87 of 1037
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