Renesas Hitachi H8S/2194 Series Hardware Manual page 8

Page Item
547 to 549
25.3.2 Master Transmit
Operation
550 to 552
25.3.3 Master Receive
Operation
556 25.3.5 Slave Transmit
Operation
561 25.3.8 Sample Flowcharts
562
565, 566 25.3.9 Initialization of Internal
State
570 to 572 25.4 Usage Notes
604 27.3.7 RTS Instruction
613 28.1.2 Block Diagram
624 28.2.5 Register Descriptions
627 28.3.2 Block Diagram
634 28.3.4 Register Descriptions
663, 664 28.4.5 Register Descriptions (4) FIFO Output Pattern Register 1 (FPDRA)
667, 668 28.4.5 Register Descriptions (9) DFG Reference Register 2 (DFCRB)
669, 670 28.4.6 Description of
Operation
688 28.6.4 Register Descriptions
Rev. 2.0, 11/00, page IV of V
Revisions (See Manual for Details)
Description amended
Figure 25.14 Flowchart for Master Transmit Mode
(Example) amended
Figure 25.15 Flowchart for Master Receive Mode
(Example) amended
Added
Description (7) to (9) added
Figure 27.15 RTS Instruction
Description amended
Stack storing
Figure 28.1 Block Diagram of Servo Circuits
Amended
(5) CTL Gain Control Register (CTLGR)
Bits 3 to 0: CTL Amplifier Gain Setting Bits
(CTLGR3 to 0) values of CTL output gain amended
Figure 28.6 REF30 Signal Generator
amended
(5) Reference Period Mode Register 2 (RFM2)
Bit 7: TBC Selection Bit
Description amended
(5) FIFO Output Pattern Register 2 (FPDRB)
Descriptions of bits in these registers added
Descriptions of bits 4 to 0 added
(11) DFG Reference Count Register (DFCTR)
Initial value of bit 4 to 0 amended and descriptions
added
Completely Amended
(5) Drum Speed Error Detection Control Register
(DFVCR)
Descriptions of bits 1 and 0 amended