Renesas Hitachi H8S/2194 Series Hardware Manual page 758

Bit 4: Drum Phase System Z
Reflects the DZp value on Z
phase system begins. If 1 was written, it is reflected on the computation, and then cleared to 0.
Set this bit after writing data to DZp.
Bit 4
DZPON Description
0 DZp value is not reflected on Z
1 DZp value is reflected on Z
Bit 3: Drum Speed System Z
Reflects the DZs value on Z
speed system begins. If 1 was written, it is reflected on the computation, and then cleared to 0.
Set this bit after writing data to DZs.
Bit 3
DZSON Description
0 DZs value is not reflected on Z
1 DZs value is reflected on Z
Bits 2 to 0: Drum System Output Gain Control Bits (DSG2, DSG1, DSG0)
Control the gain output to DRMPWM.
Bit 2 Bit 1
DSG2 DSG1
0 0
1
1 0
1
Note: Setting optional
*
-1
Initialization Bit (DZPON)
-1
of the phase system when computation processing of the drum
-1
of the phase system
-1
of the phase system
-1
Initialization Bit (DZSON)
-1
of the speed system when computation processing of the drum
-1
of the speed system
-1
of the speed system
Bit 0
DSG0 Description
× 1
0
× 2
1
× 4
0
× 8
1
× 16
0
1 (× 32)*
0 (× 64)*
1 Invalid (Do not set)
(Initial value)
(Initial value)
(Initial value)
Rev. 2.0, 11/00, page 731 of 1037