Renesas Hitachi H8S/2194 Series Hardware Manual page 803

RESET
REF30X
UP/DOWN counter (12 bits)
s/4
REC-CTL rise timing
REF30X
Counter
reset
Counter
REC-CTL
Rev. 2.0, 11/00, page 776 of 1037
Clear
RCDR1
(12bit)
Upper 12 bits
Compare
REC-CTL 1 pulse,
ASM fall timing
Match detection
RCDR1
Figure 28.60 REC-CTL Signal Generation Timing
Internal bus
W W
RCDR2or4 RCDR3or5
(12bit) (12bit)
Compare Compare
Match detection
RCDR2 (VISS/VASS S1 pulse)
RCDR3 (VISS/VASS L1 pulse, or ASM)
RCDR4 (VISS/VASS S0 pulse)
RCDR5 (VISS/VASS L0 pulse)
W
REC-CTL 0 pulse fall
timing
End of writing of one CTL
pulse (except VISS) IRRCTL