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28.9.4
Register Descriptions
(1) Capstan Phase Preset Data Registers (CPPR1, CPPR2)
CPPR1
Bit :
7
—
1
Initial value :
—
R/W :
CPPR2
15
Bit :
Initial value :
0
R/W :
W
The 20-bit preset data that defines the specified capstan phase is set in CPPR1 and CPPR2. The
20 bits are weighted as follows. Bit 3 of CPPR1 is the MSB. Bit 0 of CPPR2 is the LSB. When
CPPR2 is written to, the 20-bit preset data, including CPPR1, is loaded into the preset circuit.
Write to CPPR1 first, and CPPR2 next. The preset data is referenced to H'80000*, and can be
calculated from the following equation.
Target phase difference = Rreference signal frequency/2
Capstan phase preset data = H'80000 − (φs/n × target phase difference)
φs:
Servo clock frequency in Hz (fosc/2)
φs/n:
Clock source of selected counter
CPPR2 is accessible by word access only. Byte access gives unassured results. Reads are
disabled. If read is attempted to CPPR1 or CPPR2, an undetermined value is read out. CPPR1
and CPPR2 are initialized to H'F0 and H'0000 by a reset, and in standby mode.
Note: * The preset data value is calculated so that the counter will reach H'80000 when the
error is zero. When the counter value is latched as error data in the capstan phase
error data registers (CPER1 and CPER2), however, it is converted to a value
referenced to H'00000.
6
5
—
—
1
1
—
—
14
13
12
11
10
0
0
0
0
0
W
W
W
W
W
4
3
—
1
0
—
W
9
8
7
6
5
0
0
0
0
0
W
W
W
W
W
Rev. 2.0, 11/00, page 713 of 1037
2
1
0
0
0
0
W
W
W
4
3
2
1
0
0
0
0
W
W
W
W
0
0
W
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