Renesas Hitachi H8S/2194 Series Hardware Manual page 599

2
(9) Notes on I C Bus Interface Stop Condition Instruction Issuance
If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load
capacitance is large, or if there is a slave device of the type that drives SCL low to effect a
wait, issue the stop condition instruction after reading SCL and determining it to be low, as
shown below.
9th clock
VIH
SCL
SDA
IRIC
Rev. 2.0, 11/00, page 572 of 1037
High period secured
As waveform rise is late,
SCL is detected as low
Figure 25.20 Timing of Stop Condition Issuance
Stop condition
[2] Stop condition instruction issuance
[1] Determination of SCL=Low