Renesas Hitachi H8S/2194 Series Hardware Manual page 982

H'D0BB: Servo Interrupt Request Register 2 SIRQR2: Servo Interrupt
Bit :
7
—
Initial value :
1
—
R/W :
Note: * Only 0 can be written to clear the flag.
H'D0E0: Start Address Register STAR: 32-Byte Buffer SCI2
Bit :
7
—
Initial value :
1
—
R/W :
H'D0E1: End Address Register EDAR: 32-Byte Buffer SCI2
Bit :
7
—
Initial value :
1
—
R/W :
6 5 4
— — —
1 1 1
— — —
6 5
— —
STA4
1 1
— —
6 5
— —
EDA4
1 1
— —
3 2
— —
1 1
— —
Vertical sync signal interrupt request bit
0 Sync signal detector (VD, noise) interrupt
request is not generated
1 Sync signal detector (VD, noise) interrupt
request is generated
4 3
STA3 STA2
0 0
R/W R/W R/W
4 3
EDA3 EDA2
0 0
R/W R/W R/W
Rev. 2.0, 11/00, page 955 of 1037
1 0
IRRSNC IRRCTL
0 0
R/(W) * R/(W) *
CTL interrupt request bit
0 CTL interrupt request is not
generated
1 CTL interrupt request is
generated
2 1 0
STA1 STA0
0 0 0
R/W R/W
2 1 0
EDA1 EDA0
0 0 0
R/W R/W