Pin Configuration; Register Configuration; Register Description - Renesas Hitachi H8S/2194 Series Hardware Manual

28.12.2 Pin Configuration

Table 28.16 summarizes the pin configuration of the additional V signal.
Table 28.16 Pin Configuration
Name
Additional V pulse pin

28.12.3 Register Configuration

Table 28.17 summarizes the register that controls the additional V signal.
Table 28.17 Register Configuration
Name
Additional V control register

28.12.4 Register Description

Additional V Control Register (ADDVR)
Bit :
7
—
Initial value :
1
—
R/W :
ADDVR is an 8-bit readable/writable register. It is initialized to H'E0 by a reset, and in standby
mode.
Bits 7 to 5: Reserved
Writes are disabled. If a read is attempted, an undefined value is read out.
Bit 4: OSCH Mask Bit (HMSK)
Masks the OSCH signal in the additional V pulse.
Abbrev. I/O
Vpulse Output
Abbrev. R/W
ADDVR R/W
6 5
HMSK
— —
1 1
— —
R/W
Function
Output of additional V signal synchronized to
VideoFF
Size
Byte
4 3 2
HiZ CUT
0 0 0
R/W R/W
Rev. 2.0, 11/00, page 741 of 1037
Initial Value Address
H'E0 H'FD06F
1 0
VPON POL
0 0
R/W R/W