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Bit 8: MlevelA Bit (MlevelA)
Used for generating an additional V signal. See section 28.12, Additional V Signal Generator,
for more information.
Bits 7 to 0: PPG Output Signal A Bits (PPGA7 to PPGA0)
Used for timing control output of port 7 (PPG).
(5) FIFO Output Pattern Register 2 (FPDRB)
Bit :
15
—
1
Initial value :
—
R/W :
Bit :
7
PPGB7
Initial value :
*
R/W :
W
Note: * Undetermined
FPDRB is a buffer register for the output pattern register of FIFO2. When the timing pattern is
written in FTPRB the output pattern data written in FPDRB is written at the same time to the
position pointed by the buffer pointer of FIFO2. Be sure to write the output pattern data in
FPDRB before writing it in FTPRB.
FPDRB is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, resulting operation is not assured. No read is valid. If a read is attempted, an
undetermined value is read out. It is not initialized by a reset, stand-by or module stop,
accordingly be sure to write data before use.
Bit 15: Reserved
It cannot be written in or read out.
Bit 14: A/D Trigger B Bit (ADTRGB)
A signal for starting the A/D converter hardware.
Bit 13: S-TRIGB Bit (STRIGB)
A signal for generating an interrupt by pattern data. When STRIGB is selected by ISEL, pattern
data changes from 0 to 1, and thus generates an interrupt.
Bit 12: NarrowFFB Bit (NarrowFFB)
Controls the Narrow Video Head.
Bit 11: VideoFFB Bit (VFFB)
Controls the Video Head.
Rev. 2.0, 11/00, page 664 of 1037
14
13
ADTRGB
STRIGB
NarrowFFB
*
*
W
W
6
5
PPGB6
PPGB5
PPGB4
*
*
W
W
12
11
10
VFFB
AFFB
*
*
*
W
W
W
4
3
2
PPGB3
PPGB2
*
*
*
W
W
W
9
8
VpulseB
MlevelB
*
*
W
W
1
0
PPGB1
PPGB0
*
*
W
W
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