Register Descriptions; System Control Register (Syscr) - Renesas Hitachi H8S/2194 Series Hardware Manual

6.2

Register Descriptions

6.2.1

System Control Register (SYSCR)

Bit :
7
—
Initial value :
0
—
R/W :
SYSCR is an 8-bit readable register that selects the interrupt control mode and the detected edge
for 10, .
Only bits 5, 4, 2 and 1 are described here; for details on the other bits, see section 3.2.2, System
Control Register (SYSCR).
SYSCR is initialized to H'00 by a reset.
Bits 5 and 4: Interrupt Control Mode (INTM1, INTM0)
These bits select one of two interrupt control modes for the interrupt controller. The INTM1 bit
must not be set to 1.
Bit 5 Bit 4
INTM1 INTM0
0 0
1
1 0
1
Bit 2 and 1: 10,
10, Pin Detected Edge Select (NMIEG1, NMIEG0)
Selects the detected edge for the 10, pin.
Bit 2 Bit 1
NIMIEG1 NIMIEG0
0 0
1
1
*
Note: Don't care
*
Rev. 2.0, 11/00, page 100 of 1037
6 5
— INTM1 INTM0
0 0
—
R/W
Interrupt Control
Mode
0
1


Description
Interrupt request generated at falling edge of
Interrupt request generated at rising edge of
Interrupt request generated at both falling and rising edges of
4 3
XRST NMIEG1
0 0
R/W R R/W
Description
Interrupts are controlled by I bit (Initial value)
Interrupts are controlled by I and UI bits and ICR
Cannot be used in this LSI
Cannot be used in this LSI
2 1 0
—
NMIEG0
0 0 0
—
R/W
10,
pin (Initial value)
10,
pin
10,
pin