Renesas Hitachi H8S/2194 Series Hardware Manual page 986

H'D101: Timer Control/Status Register X TCSRX: Timer X1
7
Bit :
ICFA
Initial value :
0
R/(W) *
R/W :
Input capture flag B
Input capture flag A
0 [Clearing conditions]
When 0 is written to ICFA after reading
ICFA = 1
1 [Setting conditions]
When FRC value is transferred to ICRA by
input capture signal
Note: * Only 0 can be written to bits 7 to 1 to clear the flags.
6 5 4
ICFB ICFC ICFD
0 0 0
R/(W) * R/(W) * R/(W) *
Output compare flag A
Input capture flag D
0 [Clearing conditions]
When 0 is written to ICFD after reading
ICFD = 1
1 [Setting conditions]
When input capture signal is generated
Input capture flag C
0 [Clearing conditions]
When 0 is written to ICFC after reading
ICFC = 1
1 [Setting conditions]
When input capture signal is generated
0 [Clearing conditions]
When 0 is written to ICFB after reading
ICFB = 1
1 [Setting conditions]
When FRC value is transferred to ICRB by
input capture signal
3 2 1
OCFA OCFB OVF
0 0 0
R/(W) * R/(W) * R/(W) *
Timer overflow
0
1
Output compare flag B
0 [Clearing conditions]
When 0 is written to OCFB after reading
OCFB = 1
1 [Setting conditions]
When FRC = OCRB
0 [Clearing conditions]
When 0 is written to OCFA after reading
OCFA = 1
1 [Setting conditions]
When FRC = OCRA
Rev. 2.0, 11/00, page 959 of 1037
0
CCLRA
0
R/ W
Counter clear
0 FRC clearing is disabled
1 FRC clearing is enabled
[Clearing conditions]
When 0 is written to OVF after reading
OVF = 1
[Setting conditions]
When FRC changes from H'FFFF to
H'0000