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Bits 1 and 0: REF30P Division Ratio Selection Bits (DVREF1, DVREF0)
Select the division value of REF30P. If it is read-accessed, the counter value is read out. (The
selected division value is set by the UDF of the counter.)
Bit 1
Bit 0
DVREF1
DVREF0
0
0
1
1
0
1
(3) X-value Data Register (XDR)
15
Bit :
—
Initial value :
1
—
R/W :
The X-value data register (XDR) is a 16-bit write-only register. No read is valid. If a read is
attempted, an undefined value is read out. XDR accepts only a word-access. If a byte access is
attempted, operation is not assured.
Set X-value correction data to XDR, except a value which is beyond the cycle of the CTL pulse.
08
If AT/
= 0, TRK/
Set an X-value and TRK correction value in PB mode, and an X-value in REC mode.
It is initialized to H'F000 by a reset, stand-by or module stop.
(4) TRK-value Data Register (TRDR)
Bit :
15
—
Initial value :
1
—
R/W :
The TRK-value data register (TRDR) is a 16-bit write-only register. No read is valid. If a read
is attempted, an undefined value is read out. TRDR accepts only a word-access. If a byte access
is attempted, operation is not assured.
Set a TRK-value correction data to TRDR, except a value which is beyond the cycle of the CTL
pulse. It is initialized to H'F000 by a reset, stand-by or module stop.
Rev. 2.0, 11/00, page 722 of 1037
Description
Division in 1
Division in 2
Division in 3
Division in 4
14
13
12
11
10
—
—
—
XD11 XD10
1
1
1
0
—
—
—
W
W
;
= 0 was set, CAPREF30 can be generated only by the setting of XDR.
14
13
12
11
10
—
—
—
TRD11 TRD10
1
1
1
0
0
—
—
—
W
W
9
8
7
6
XD9 XD8
XD7 XD6
0
0
0
0
0
W
W
W
W
9
8
7
6
TRD9 TRD8
TRD7 TRD6
0
0
0
0
W
W
W
W
(Initial value)
5
4
3
2
XD5 XD4
XD3 XD2
XD1 XD0
0
0
0
0
W
W
W
W
5
4
3
2
TRD5 TRD4
TRD3 TRD2
TRD1 TRD0
0
0
0
0
W
W
W
W
1
0
0
0
W
W
1
0
0
0
W
W
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