Renesas Hitachi H8S/2194 Series Hardware Manual page 748

Bit 5: Capstan Phase Correction Auto/Manual Selection Bit (AT/
Selects whether the generation of the correction reference signal (CAPREF30) for capstan phase
control is controlled automatically or manually depending on the status of the ASM and REC/
bits of the CTL mode register.
Bit 5
&
&
AT/ Description
0 Manual mode
1 Auto mode
Bit 4: Capstan Phase Correction Register Selection Bit (TRK/
Determines the method to generate the CAPREF30 signal when the AT/
Bit 4
; ;
TRK/ Description
0 Generates CAPREF30 only by the set value of XDR
1 Generates CAPREF30 by the set values of XDR and TRDR
Bit 3: Reference Signal Selection Bit (EXC/REF)
Selects the reference signal to generate the correction reference signal (CAPREF30).
Bit 3
EXC/REF Description
0 Generates the signal based on REF30P
1 Generates the signal based on the external reference signal
Bit 2: Clock Source Selection Bit (XCS)
Selects the clock source to be supplied to the 10-bit counter.
Bit 2
XCS Description
φs
0
φs/2
1
08
08
)
(Initial value)
; ;
)
08
bit is 0.
(Initial value)
(Initial value)
(Initial value)
Rev. 2.0, 11/00, page 721 of 1037
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